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path: root/drivers/gpu/drm/i915/intel_ddi.c
AgeCommit message (Expand)AuthorFilesLines
2015-12-01drm/i915: Don't use crtc->config when reading out infoframe stateVille Syrjälä1-1/+1
2015-11-23Merge tag 'v4.4-rc2' into drm-intel-next-queuedDaniel Vetter1-10/+65
2015-11-18drm/i915: Type safe register read/writeVille Syrjälä1-6/+7
2015-11-18drm/i915: Consider SPLL as another shared pll, v2.Maarten Lankhorst1-10/+65
2015-11-17drm/i915: Make turning on/off PW1 and Misc I/O part of the init/fini sequencesDamien Lespiau1-2/+2
2015-11-13drm/i915/skl: Update DDI translation tables for SKLjim.bride@linux.intel.com1-11/+11
2015-11-13drm/i915: Fix SKL i_boost levelAnder Conselvan de Oliveira1-3/+3
2015-11-10drm/i915: Setup DDI clk for MST on SKLVille Syrjälä1-20/+29
2015-11-09drm/i915/bxt: Force port A DDI to use 4 lanesMatt Roper1-0/+14
2015-11-05drm/i915: Create intel_dp->prepare_link_retrain() hookAnder Conselvan de Oliveira1-4/+4
2015-10-28drm/i915/kbl: Introduce Kabylake platform defition.Rodrigo Vivi1-8/+8
2015-10-26drm/i915: Use paramtrized WRPLL_CTL()Ville Syrjälä1-4/+4
2015-10-21drm/i915: add helpers for platform specific revision id range checksJani Nikula1-2/+1
2015-10-21drm/i915/bxt: add revision id for A1 stepping and use itJani Nikula1-1/+1
2015-10-21drm/i915/skl: If needed sanitize bios programmed cdclkShobhit Kumar1-2/+2
2015-10-06drm/i915: Rename DP link training functionsAnder Conselvan de Oliveira1-1/+0
2015-10-02drm/i915/bxt: DSI encoder support in CRTC modesetShashank Sharma1-2/+5
2015-10-01drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.Ville Syrjälä1-8/+8
2015-09-30drm/i915: s/_FDI_RXA_.../FDI_RX_...(PIPE_A)/Ville Syrjälä1-23/+23
2015-09-30drm/i915/ddi: use switch case instead of if ladder for ddi_get_encoder_portJani Nikula1-7/+13
2015-09-30drm/i915/ddi: warn instead of oops on invalid ddi encoder typeJani Nikula1-2/+1
2015-09-30drm/i915/bxt: Set oscaledcompmethod to enable scale valueSonika Jindal1-2/+6
2015-09-30drm/i915/bxt: eDP low vswing supportSonika Jindal1-4/+19
2015-09-23drm/i915: Parametrize DDI_BUF_TRANS registersVille Syrjälä1-10/+9
2015-09-18drm/i915/bxt: Fix wrongly placed ')' in I915_READ()Damien Lespiau1-1/+1
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter1-50/+25
2015-09-01drm/i915: Don't use link_bw for PLL setupVille Syrjälä1-7/+4
2015-08-26drm/i915: Put back lane_count into intel_dp and add link_rate tooVille Syrjälä1-2/+3
2015-08-26drm/i915/skl: Update DDI buffer translation programming.Rodrigo Vivi1-50/+25
2015-08-14drm/i915: Move intel_dp->lane_count into pipe_configVille Syrjälä1-4/+6
2015-08-14drm/i915: Don't pass clock to DDI PLL select functionsVille Syrjälä1-10/+10
2015-08-14drm/i915: Don't use link_bw for PLL setupVille Syrjälä1-7/+4
2015-08-14drm/i915/bxt: WA for swapped HPD pins in A steppingSonika Jindal1-1/+9
2015-08-14drm/i915: Per-DDI I_boost overrideAntti Koskipaa1-8/+30
2015-08-14drm/i915: Set alternate aux for DDI-ERodrigo Vivi1-3/+2
2015-07-06drm/i915: set FDI translations to NULL on SKLPaulo Zanoni1-0/+1
2015-07-06drm/i915/bxt: BUNs related to port PLLVandana Kannan1-10/+5
2015-07-06drm/i915: Fix HDMI 12bpc and pixel repeat clock readout for DDI platformsVille Syrjälä1-25/+24
2015-07-03drm/i915/bxt: mask off the DPLL state checker bits we don't programImre Deak1-0/+20
2015-06-30drm/i915/bxt: add DDI port HW readout supportImre Deak1-2/+20
2015-06-30drm/i915/bxt: add missing DDI PLL registers to the state checkingImre Deak1-3/+13
2015-06-30drm/i915/skl: Buffer translation improvementsDavid Weinehall1-115/+394
2015-06-26drm/i915/skl: Skip remaining dividers when deviation is 0Damien Lespiau1-1/+8
2015-06-26drm/i915/skl: Prefer even dividers for SKL DPLLsDamien Lespiau1-0/+7
2015-06-26drm/i915/skl: Replace the HDMI DPLL divider computation algorithmDamien Lespiau1-74/+137
2015-06-12drm/i915/bxt: fix DDI PHY vswing scale value settingImre Deak1-18/+18
2015-06-12drm/i915: Don't display the boot CDCLK twiceDamien Lespiau1-4/+3
2015-06-03drm/i915/bxt: edp1.4 Intermediate Freq supportSonika Jindal1-23/+16
2015-05-29drm/i915/skl: Don't try to store the wrong central frequencyDamien Lespiau1-2/+0
2015-05-29drm/i915: Correctly prefix HSW/BDW HDMI clock functionsDamien Lespiau1-13/+12
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