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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2019-05-28drm/i915: Enable infoframes on GLK+ for HDRVille Syrjälä1-1/+4
2019-05-28drm/i915/guc: Correctly handle GuC interrupts on Gen11Oscar Mateo1-0/+4
2019-05-27drm/i915: Make sure we have enough memory bandwidth on ICLVille Syrjälä1-0/+3
2019-05-27drm/i915/icl: Fix AUX-B HW not done issue w/o AUX-AImre Deak1-0/+3
2019-05-27drm/i915: make REG_BIT() and REG_GENMASK() work with variablesJani Nikula1-3/+3
2019-05-24drm/i915/gen11: enable support for headerless msgsDongwon Kim1-0/+1
2019-05-23drm/i915/dp: Add a support of YCBCR 4:2:0 to DP MSAGwan-gyeong Mun1-0/+1
2019-05-22drm/i915/icl: Add WaDisableBankHangModeTvrtko Ursulin1-0/+3
2019-05-02drm/i915/icl: Factor out combo PHY lane power setup helperImre Deak1-1/+0
2019-05-02drm/i915: hsw+ audio regs are per-transocderVille Syrjälä1-6/+6
2019-04-30drm/i915: Enable pipe HDR mode on ICL if only HDR planes are usedVille Syrjälä1-0/+1
2019-04-26drm/i915: Enable render context support for gen4 (Broadwater to Cantiga)Chris Wilson1-0/+1
2019-04-17drm/i915: add GEN2_ prefix to the I{E, I, M, S}R registersPaulo Zanoni1-4/+4
2019-04-12drm/i915: Handle catastrophic error on engine resetMika Kuoppala1-2/+4
2019-04-11drm/i915: Use Engine1 instance for gen11 pm interruptsMika Kuoppala1-0/+5
2019-04-11drm/i915/icl: Enable media sampler powergateMika Kuoppala1-2/+3
2019-04-08drm/i915: Remove unused VLV/CHV PSR registersJosé Roberto de Souza1-36/+0
2019-04-05drm/i915: Make RING_PDP relative to engine->mmio_baseChris Wilson1-2/+2
2019-04-03drm/i915: Add "10.6" LUT mode for i965+Ville Syrjälä1-0/+4
2019-04-03drm/i915: Add 10bit LUT for ilk/snbVille Syrjälä1-0/+9
2019-04-03drm/i915: Don't use split gamma when we don't have toVille Syrjälä1-0/+2
2019-03-29drm/i915: Program EXT2 GC MAX registersUma Shankar1-0/+1
2019-03-27drm/i915/icl: Fix VEBOX mismatch BUG_ON()José Roberto de Souza1-1/+1
2019-03-26drm/i915: take a reference to uncore in the engine and use itDaniele Ceraolo Spurio1-8/+8
2019-03-21drm/i915: Use __is_constexpr()Chris Wilson1-2/+2
2019-03-20drm/i915/icl: Fix the TRANS_DDI_FUNC_CTL2 bitfield macroManasi Navare1-1/+1
2019-03-19drm/i915: Fix readout for cnl DPLL kdiv==3Ville Syrjälä1-1/+1
2019-03-18drm/i915: use REG_FIELD_PREP() to define register bitfield valuesJani Nikula1-30/+39
2019-03-18drm/i915: deprecate _SHIFT in favor of _MASK passed to accessorsJani Nikula1-15/+30
2019-03-18drm/i915: introduce REG_BIT() and REG_GENMASK() to define register contentsJani Nikula1-33/+61
2019-03-14drm/i915/icl+: Always use TPS2 or TPS3 when exiting PSR1José Roberto de Souza1-0/+1
2019-03-11Merge tag 'topic/hdr-formats-2019-03-07' of git://anongit.freedesktop.org/drm...Joonas Lahtinen1-0/+9
2019-03-11drm/i915/icl: Fix CRC mismatch error for DP link layer complianceAditya Swarup1-6/+7
2019-03-08drm/i915: Read out memory typeVille Syrjälä1-0/+13
2019-03-08drm/i915: Extract DIMM info on cnl+Ville Syrjälä1-2/+15
2019-03-08drm/i915: Fix DRAM size reporting for BXTVille Syrjälä1-5/+5
2019-03-05drm/i915: Store the BIT(engine->id) as the engine's maskChris Wilson1-12/+12
2019-03-05drm/i915/icl: Add Y2xx and Y4xx (xx:10/12/16) plane control definitionsSwati Sharma1-0/+6
2019-03-05drm/i915: Add P010, P012, P016 plane control definitionsJuha-Pekka Heikkila1-0/+3
2019-03-05drm/i915: Fix bit name in PP_STATUS registerLucas De Marchi1-1/+1
2019-02-26drm/i915: Add the missing HDMI gamut metadata packet stuffVille Syrjälä1-3/+5
2019-02-21drm/i915/icl: Drop redundant gamma mode maskUma Shankar1-1/+0
2019-02-20drm/i915: Extend skl+ crc sources with more planesVille Syrjälä1-0/+9
2019-02-14drm/i915: Include "ignore lines" in skl+ wm stateVille Syrjälä1-0/+1
2019-02-14Revert "drm/i915: W/A for underruns with WM1+ disabled on icl"Ville Syrjälä1-1/+0
2019-02-14drm/i915: Make MG PHY macros semantically consistentAditya Swarup1-25/+25
2019-02-14drm/i915: Make combo PHY DDI macro definitions consistent for ICL and CNLAditya Swarup1-3/+3
2019-02-13drm/i915: Assert that VED and ISP are power gatedVille Syrjälä1-0/+28
2019-02-13drm/i915: s/PUNIT_REG_DSPFREQ/PUNIT_REG_DSPSSPM/Ville Syrjälä1-1/+1
2019-02-13drm/i915/icl: Enable pipe output cscUma Shankar1-0/+65
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