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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2020-12-04drm/i915: Add VRR_CTL_LINE_COUNT field to VRR_CTL register defManasi Navare1-0/+1
2020-12-02drm/i915: remove last traces of I915_READ(), I915_WRITE() and POSTING_READ()Jani Nikula1-2/+4
2020-11-19drm/i915/perf: workaround register corruption in OATAILPTRLionel Landwerlin1-0/+2
2020-11-09drm/i915/dg1: map/unmap pll clocksLucas De Marchi1-0/+24
2020-10-30drm/i915: Enable hpd logic only for ports that are presentVille Syrjälä1-17/+0
2020-10-30drm/i915: Remove per-platform IIR HPD maskingVille Syrjälä1-12/+3
2020-10-30drm/i915: s/tc_port/hpd_pin/ in icp+ TC hotplug bitsVille Syrjälä1-20/+20
2020-10-30drm/i915: s/tc_port/hpd_pin/ in GEN11_{TC,TBT}_HOTPLUG()Ville Syrjälä1-18/+19
2020-10-30drm/i915: s/port/hpd_pin/ for icp+ ddi hpd bitsVille Syrjälä1-25/+25
2020-10-30drm/i915: Introduce GEN8_DE_PORT_HOTPLUG()Ville Syrjälä1-5/+5
2020-10-30drm/i915: Parametrize BXT_DE_PORT_HP_DDI with hpd_pinVille Syrjälä1-6/+6
2020-10-30drm/i915: s/PORT_TC/TC_PORT_/Ville Syrjälä1-30/+30
2020-10-29drm/i915: Use _MMIO_PIPE3() for ilk+ WM0_PIPE registersVille Syrjälä1-4/+5
2020-10-24drm/i915/dg1: invert HPD pinsClinton A Taylor1-0/+4
2020-10-24drm/i915/dg1: add hpd interrupt handlingLucas De Marchi1-0/+8
2020-10-21drm/i915: Introduce scaling filter related registers and bit fieldsPankaj Bharadiya1-0/+22
2020-10-20drm/i915: Sort the mess around ICP TC hotplugs regsVille Syrjälä1-107/+106
2020-10-20drm/i915/display: Program DBUF_CTL tracker state serviceJosé Roberto de Souza1-5/+9
2020-10-16drm/i915/dg1: Update DMC_DEBUG registerAnshuman Gupta1-0/+1
2020-10-16drm/i915/dg1: Add initial DG1 workaroundsStuart Summers1-5/+9
2020-10-16drm/i915/dg1: Enable DPLL for DG1Lucas De Marchi1-0/+4
2020-10-16drm/i915/dg1: Add DPLL macros for DG1Aditya Swarup1-1/+16
2020-10-10drm/i915: Rename FORCEWAKE_BLITTER to FORCEWAKE_GTMatt Roper1-2/+2
2020-10-06drm/i915/skl: Work around incorrect BIOS WRPLL PDIV programmingImre Deak1-0/+1
2020-10-06drm/i915/dg1: Wait for pcode/uncore handshake at startupMatt Roper1-0/+3
2020-10-01drm/i915: Implement display WA #1142:kbl,cfl,cmlVille Syrjälä1-0/+3
2020-09-28drm/i915: Relocate CHV CGM gamma masksVille Syrjälä1-3/+6
2020-09-28drm/i915: Add support for async flips in I915Karthik B S1-0/+1
2020-09-15drm/i915: Nuke the redundant TC/TBT HPD bit definesVille Syrjälä1-24/+12
2020-09-11drm/i915: Nuke dpio_phy_iosf_port[]Ville Syrjälä1-1/+0
2020-08-26drm/i915/gt: Implement WA_1406941453Clint Taylor1-0/+1
2020-08-17drm/i915/display: Implement WA 1408330847José Roberto de Souza1-0/+1
2020-08-17drm/i915/tgl: Set subplatformsJosé Roberto de Souza1-0/+6
2020-08-17drm/i915/tgl: Fix TC-cold block/unblock sequenceImre Deak1-2/+2
2020-08-17Revert "drm/i915/rkl: Add Wa_14011224835 for PHY B initialization"Matt Roper1-12/+1
2020-08-17drm/i915: Implement WA 14011294188José Roberto de Souza1-0/+1
2020-08-17drm/i915/rkl: Add Wa_14011224835 for PHY B initializationMatt Roper1-1/+12
2020-08-17drm/i915/rkl: Handle HTIMatt Roper1-0/+6
2020-08-17drm/i915/rkl: Add DPLL4 supportMatt Roper1-2/+4
2020-08-17drm/i915/rkl: Handle new DPCLKA_CFGCR0 layoutMatt Roper1-0/+6
2020-08-17drm/i915/display: Implement HOBLJosé Roberto de Souza1-0/+2
2020-07-14drm/i915/dg1: add support for the master unit interruptLucas De Marchi1-0/+4
2020-07-07drm/i915/display: Implement new combo phy initialization stepJosé Roberto de Souza1-0/+9
2020-07-06drm/i915: Fix spelling mistake in i915_reg.hFlavio Suligoi1-2/+2
2020-07-03drm/i915/fbc: Allow FBC to recompress after a 3D workload on i85x/i865Ville Syrjälä1-0/+1
2020-07-01drm/i915: Add PSR2 selective fetch registersJosé Roberto de Souza1-5/+63
2020-06-30drm/i915/fbc: Parametrize FBC_CONTROLVille Syrjälä1-7/+11
2020-06-27drm/i915/gen12: implement Wa_14011508470Matt Atwood1-0/+6
2020-06-25Merge drm/drm-next into drm-intel-next-queuedJani Nikula1-1/+1
2020-06-16drm/i915/gt: Move ivb GT workarounds from init_clock_gating to workaroundsChris Wilson1-1/+1
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