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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2018-03-07drm/i915/icl: Correctly initialize the Gen11 enginesOscar Mateo1-0/+6
2018-03-02drm/i915: Add support for the YCbCr COLOR_RANGE propertyVille Syrjälä1-0/+4
2018-03-02drm/i915: Add support for the YCbCr COLOR_ENCODING propertyVille Syrjälä1-1/+4
2018-03-02drm/i915: Fix plane YCbCr->RGB conversion for GLKVille Syrjälä1-0/+5
2018-03-02drm/i915: Correctly handle limited range YCbCr data on VLV/CHVVille Syrjälä1-0/+10
2018-03-01drm/i915/icl: Prepare for more ringsTvrtko Ursulin1-1/+4
2018-03-01Merge drm-next into drm-intel-next-queued (this time for real)Joonas Lahtinen1-0/+85
2018-03-01Merge tag 'drm-intel-next-2018-02-21' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-19/+60
2018-02-23drm/i915: Add enum aux_ch and clean up the aux init to use itVille Syrjälä1-4/+4
2018-02-22drm/i915/hsw: add missing disabled EUs registers readsLionel Landwerlin1-0/+7
2018-02-16drm/i915/cnl: Fix PORT_TX_DW5/7 register addressMahesh Kumar1-2/+2
2018-02-16Merge tag 'topic/hdcp-2018-02-13' of git://anongit.freedesktop.org/drm/drm-mi...Dave Airlie1-0/+85
2018-02-13drm/i915/icl: Enable both DBuf slices during initMahesh Kumar1-0/+2
2018-02-13drm/i915/icl: implement the display init/uninit sequencesPaulo Zanoni1-2/+14
2018-02-13drm/i915/icl: add the main CDCLK functionsPaulo Zanoni1-15/+20
2018-02-13drm/i915/icl: add ICL support to cnl_set_procmon_ref_valuesPaulo Zanoni1-0/+22
2018-02-05drm/i915: fix misalignment in HDCP register defRamalingam C1-29/+29
2018-01-31drm/i915/icl: Set graphics mode register for gen11Kelvin Gardiner1-0/+2
2018-01-31drm/i915/icl: Handle expanded PLANE_CTL_FORMAT fieldJames Ausmus1-0/+6
2018-01-31drm/i915/icl: Introduce MBus related registersMahesh Kumar1-0/+25
2018-01-30drm/i915/cnl: Enable DDI-F on Cannonlake.Rodrigo Vivi1-0/+2
2018-01-30drm/i915: Fix DPLCLKA_CFGCR0 bits for Port F.Rodrigo Vivi1-4/+6
2018-01-30drm/i915/cnl: Fix _CNL_PORT_TX_DW2_LN0_F definition.Rodrigo Vivi1-1/+1
2018-01-30drm/i915/cnl: Extend Wa 1178 to Aux F.Rodrigo Vivi1-1/+3
2018-01-30drm/i915/cnl: Add AUX-F supportRodrigo Vivi1-0/+9
2018-01-24drm/i915: Implement display w/a #1143Ville Syrjälä1-2/+6
2018-01-24drm/i915/cnl: Fix aux selection for WA 1178Rodrigo Vivi1-1/+1
2018-01-20drm/i915/psr: Don't name status or debug registers like control registers.Dhinakaran Pandiyan1-3/+3
2018-01-19drm/i915/icl: Icelake interrupt register addresses and bitsTvrtko Ursulin1-0/+63
2018-01-19drm/i915/icp: add ICP gmbus and gpio supportAnusha Srivatsa1-1/+6
2018-01-19drm/i915/icp: Get/set proper Raw clock frequency on ICPAnusha Srivatsa1-0/+2
2018-01-19drm/i915: Extending HDCP for HSW, BDW and BXT+Ramalingam C1-0/+1
2018-01-18drm/i915/cnl: apply Display WA #1178 to fix type C donglesLucas De Marchi1-0/+11
2018-01-10drm/i915: Stop getting the fault address from RING_FAULT_REGOscar Mateo1-0/+2
2018-01-08drm/i915: Implement HDCP for HDMISean Paul1-0/+1
2018-01-08drm/i915: Add function to output Aksv over GMBUSSean Paul1-0/+1
2018-01-08drm/i915: Add HDCP framework + base implementationSean Paul1-0/+83
2018-01-05drm/i915: Whitelist SLICE_COMMON_ECO_CHICKEN1 on Geminilake.Kenneth Graunke1-0/+2
2017-12-23drm/i915: Apply Display WA #1183 on skl, kbl, and cflLucas De Marchi1-0/+2
2017-12-22drm/i915: Disable GMBUS clock gating around GMBUS transfers on gen9+Ville Syrjälä1-0/+4
2017-12-22drm/i915: Clean up the PNV bit banging vs. GMBUS clock gating w/aVille Syrjälä1-0/+1
2017-12-20drm/i915: Implement WaDisableEarlyEOT.Rafael Antognolli1-0/+1
2017-12-20drm/i915: Implement WaDisableVFclkgate.Rafael Antognolli1-0/+3
2017-12-19drm/i915/cnl: Add support for horizontal plane flippingJoonas Lahtinen1-0/+1
2017-11-22drm/i915/pmu: Expose a PMU interface for perf queriesTvrtko Ursulin1-0/+3
2017-11-17Revert "drm/i915: Display WA #1133 WaFbcSkipSegments:cnl, glk"Radhakrishna Sripada1-3/+0
2017-11-15drm/i915: Check if the stolen memory "reserved" area is enabled or notVille Syrjälä1-0/+2
2017-11-14drm/i915: Display WA #1185 WaDisableDARBFClkGating:cnl, glkRodrigo Vivi1-0/+1
2017-11-14drm/i915/glk: Refactor handling of PLANE_COLOR_CTL for GLK+James Ausmus1-4/+8
2017-11-13drm/i915: There is only one fault register from GEN8 onwardsMichel Thierry1-0/+2
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-25 14:55:52 +0300