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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2018-06-19drm/i915: Enable provoking vertex fix on Gen9 systems.Kenneth Graunke1-0/+5
2018-05-13drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glkMichel Thierry1-0/+3
2018-05-11drm/i915/icl: WaForwardProgressSoftResetOscar Mateo1-0/+5
2018-05-11drm/i915/icl: Wa_1406838659Oscar Mateo1-0/+3
2018-05-11drm/i915/icl: Wa_1604302699Oscar Mateo1-1/+3
2018-05-11drm/i915/icl: Wa_1405779004Oscar Mateo1-0/+1
2018-05-11drm/i915/icl: WaDisCtxReloadOscar Mateo1-0/+3
2018-05-11drm/i915/icl: WaCL2SFHalfMaxAllocOscar Mateo1-0/+4
2018-05-11drm/i915/icl: WaDisableCleanEvictsOscar Mateo1-2/+3
2018-05-11drm/i915/icl: WaModifyGamTlbPartitioningOscar Mateo1-0/+5
2018-05-11drm/i915/icl: WaL3BankAddressHashingOscar Mateo1-0/+6
2018-05-11drm/i915/icl: WaGAPZPrioritySchemeOscar Mateo1-2/+3
2018-05-11drm/i915/icl: Enable Sampler DFROscar Mateo1-0/+3
2018-05-11drm/i915/icl: Introduce initial Icelake WorkaroundsOscar Mateo1-0/+1
2018-05-04drm/i915/icl: Add configuring MOCS in new Icelake enginesTomasz Lis1-0/+2
2018-04-28drm/i915/icl: add definitions for the ICL PLL registersPaulo Zanoni1-0/+149
2018-04-28drm/i915/icl: update ddb entry start/end mask during hw ddb readoutMahesh Kumar1-0/+3
2018-04-27drm/i915/icl: Don't set pipe CSC/Gamma in PLANE_COLOR_CTLJames Ausmus1-2/+2
2018-04-27drm/i915/psr/skl+: Print information about what caused a PSR exitJosé Roberto de Souza1-0/+23
2018-04-21drm/i915: Enable edp psr error interrupts on bdw+Ville Syrjälä1-3/+4
2018-04-21drm/i915: Enable edp psr error interrupts on hswDaniel Vetter1-0/+8
2018-04-09drm/i915: Set scaler mode for NV12Chandra Konduru1-0/+2
2018-04-09drm/i915: Display WA 827Vidya Srinivas1-0/+3
2018-04-06drm/i915/icl: Handle RPS interrupts correctly for Gen11Oscar Mateo1-0/+1
2018-04-06drm/i915/icl: Use hw engine class, instance to find irq handlerMika Kuoppala1-1/+3
2018-04-06drm/i915/icl: Add reset control register changesMichel Thierry1-0/+11
2018-03-30Merge airlied/drm-next into drm-intel-next-queuedRodrigo Vivi1-1/+23
2018-03-30drm/i915/psr: Use PSR2 macro for PSR2José Roberto de Souza1-1/+2
2018-03-30drm/i915/psr/cnl: Enable Y-coordinate support in sourceJosé Roberto de Souza1-0/+3
2018-03-29drm/i915: rename PPGTT/GGTT fields OA registersLionel Landwerlin1-3/+3
2018-03-28drm/i915/gen11: add support for reading the timestamp frequencyPaulo Zanoni1-0/+6
2018-03-24drm/i915: protect macro parameters in SWING_SEL_{UPP,LO}WERPaulo Zanoni1-2/+2
2018-03-24drm/i915/icl: Add register defs for voltage swing sequences for MG PHY DDIManasi Navare1-0/+116
2018-03-24drm/i915/icl: Add register definitions for Combo PHY vswing sequences.Manasi Navare1-0/+44
2018-03-21drm/i915/psr: Remove open-coded PSR AUX transactions for SKL+Dhinakaran Pandiyan1-0/+6
2018-03-21drm/i915/icl: Added ICL 11 slice, subslice and EU fuse detectionKelvin Gardiner1-0/+8
2018-03-20drm/i915/icl: Update subslice define for ICL 11Kelvin Gardiner1-0/+4
2018-03-20drm/i915/icl: Check for fused-off VDBOX and VEBOX instancesOscar Mateo1-0/+5
2018-03-16drm/i915: Kill the remaining CHV HBR2 leftoversVille Syrjälä1-2/+0
2018-03-15drm/i915: Split GPU commands definitions into separate headerMichal Wajdeczko1-263/+0
2018-03-15drm/i915/cnl: Kill _MMIO_PORT6 macroMahesh Kumar1-5/+5
2018-03-15drm/i915/cnl; Add macro to get PORT_TX registerMahesh Kumar1-98/+39
2018-03-14Merge tag 'drm-intel-next-2018-03-08' of git://anongit.freedesktop.org/drm/dr...Dave Airlie1-5/+34
2018-03-14Merge tag 'drm-misc-next-2018-03-09-3' of git://anongit.freedesktop.org/drm/d...Dave Airlie1-1/+23
2018-03-14drm/i915/psr: Comment to clarify SRD_DEBUG is called PSR_MASK SKL+Dhinakaran Pandiyan1-2/+2
2018-03-14drm/i915: Move CUR SURFLIVE definition to a better place.Rodrigo Vivi1-3/+2
2018-03-12drm/i915/psr: Display WA 0884 applied broadly for more HW tracking.Rodrigo Vivi1-0/+3
2018-03-08drm/i915/cnl: Add Wa_2201832410Rodrigo Vivi1-0/+3
2018-03-07drm/i915/icl: Gen11 forcewake supportDaniele Ceraolo Spurio1-0/+4
2018-03-07drm/i915/icl: new context descriptor supportDaniele Ceraolo Spurio1-0/+6
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