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path: root/drivers/gpu/drm/i915/i915_reg.h
AgeCommit message (Expand)AuthorFilesLines
2016-09-15drm/i915: Fix hpd live status bits for g4xVille Syrjälä1-7/+8
2016-07-27drm/i915: Update CDCLK_FREQ register on BDW after changing cdclk frequencyVille Syrjälä1-0/+2
2016-05-11drm/i915: Make RPS EI/thresholds multiple of 25 on SNB-BDWVille Syrjälä1-1/+8
2015-10-13drm/i915: Parametrize and fix SWF registersVille Syrjälä1-14/+14
2015-10-13drm/i915: s/PIPE_FRMCOUNT_GM45/PIPE_FRMCOUNT_G4X/ etc.Ville Syrjälä1-6/+6
2015-10-13drm/i915: Fix a few bad hex numbers in register definesVille Syrjälä1-2/+2
2015-10-13drm/i915: Protect register macro argumentsVille Syrjälä1-46/+46
2015-10-13drm/i915: Include gpio_mmio_base in GMBUS reg definesVille Syrjälä1-6/+6
2015-10-13drm/i915: Parametrize HSW video DIP data registersVille Syrjälä1-8/+8
2015-10-13drm/i915: Eliminate weird parameter inversion from BXT PPS registersVille Syrjälä1-4/+4
2015-10-07drm/i915/bxt: Set time interval unit to 0.833usAkash Goel1-1/+4
2015-10-06drm/i915: Add GEN7_GPGPU_DISPATCHDIMX/Y/Z to the register whitelistJordan Justen1-0/+4
2015-10-02drm/i915/bxt: Modify BXT BLC according to VBT changesSunil Kamath1-8/+20
2015-10-02drm/i915/bxt: Program Tx Rx and Dphy clocksShashank Sharma1-0/+62
2015-10-02drm/i915/bxt: DSI enable for BXTShashank Sharma1-0/+7
2015-10-02drm/i915: rename INSTDONE1 to GEN4_INSTDONE1Imre Deak1-1/+1
2015-10-02drm/i915: rename INSTDONE to GEN2_INSTDONEImre Deak1-1/+2
2015-10-02drm/i915: remove duplicate names for the render ring INSTDONE registerImre Deak1-2/+4
2015-10-01drm/i915: s/GET_CFG_CR1_REG/DPLL_CFGCR1/ etc.Ville Syrjälä1-2/+2
2015-09-30drm/i915/bdw: Check for slice, subslice and EU count for BDWŁukasz Daniluk1-0/+18
2015-09-30drm/i915: Read czclk from CCK on vlv/chvVille Syrjälä1-0/+1
2015-09-30drm/i915: Renaming CCK related reg definitionsVandana Kannan1-5/+5
2015-09-30drm/i915: Add VLV_HDMIB etc. which already include VLV_DISPLAY_BASEVille Syrjälä1-1/+7
2015-09-30drm/i915: Parametrize PALETTE and LGC_PALETTEVille Syrjälä1-3/+3
2015-09-30drm/i915: Include MCHBAR_MIRROR_BASE in ILK_GDSRVille Syrjälä1-1/+1
2015-09-30drm/i915: Add LO/HI PRIVATE_PAT registersVille Syrjälä1-1/+2
2015-09-30drm/i915: Parametrize fence registersVille Syrjälä1-5/+13
2015-09-30drm/i915/bxt: Set oscaledcompmethod to enable scale valueSonika Jindal1-1/+2
2015-09-23drm/i915: Parametrize DDI_BUF_TRANS registersVille Syrjälä1-1/+2
2015-09-23drm/i915: Parametrize TV luma/chroma filter registersVille Syrjälä1-8/+4
2015-09-23drm/i915: Parametrize ILK turbo registersVille Syrjälä1-5/+5
2015-09-23drm/i915: Parametrize FBC_TAG registersVille Syrjälä1-1/+1
2015-09-23drm/i915: Parametrize GEN7_GT_SCRATCH and GEN7_LRA_LIMITSVille Syrjälä1-2/+2
2015-09-23drm/i915: Implement stolen reserved detection for ctg/elkVille Syrjälä1-0/+5
2015-09-23drm/i915/bxt: DSI prepare changes for BXTShashank Sharma1-0/+21
2015-09-23drm/i915/bxt: Enable BXT DSI PLLShashank Sharma1-0/+22
2015-09-14drm/i915/gen9: WA ST Unit Power Optimization DisableRobert Beckett1-0/+3
2015-09-14drm/i915/bxt: Add WaSetClckGatingDisableMediaArun Siluvery1-0/+1
2015-09-07drm/i915: initialize backlight max from VBTJani Nikula1-0/+3
2015-09-02drm/i915: Rewrite BXT HPD code to conform to pre-existing styleVille Syrjälä1-15/+0
2015-09-02drm/i915: Add port A HPD support for SPTVille Syrjälä1-1/+3
2015-09-02drm/i915: Rename BXT PORTA HPD definesVille Syrjälä1-5/+5
2015-09-02drm/i915: Clean up various HPD definesVille Syrjälä1-36/+38
2015-09-02Merge tag 'drm-intel-next-fixes-2015-09-02' into drm-intel-next-queuedDaniel Vetter1-0/+12
2015-09-01drm/i915: Add CHV PHY LDO power sanity checksVille Syrjälä1-0/+2
2015-09-01drm/i915: Add some CHV DPIO lane power state assertsVille Syrjälä1-0/+8
2015-08-26drm/i915: Force CL2 off in CHV x1 PHYVille Syrjälä1-0/+1
2015-08-26drm/i915: Enable DPIO SUS clock gating on CHVVille Syrjälä1-0/+4
2015-08-26drm/i915: Implement PHY lane power gating for CHVVille Syrjälä1-0/+8
2015-08-26drm/i915/skl: enable DDI-E hotplugXiong Zhang1-0/+12
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