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path: root/drivers/gpu/drm/i915/gt/intel_engine_cs.c
AgeCommit message (Expand)AuthorFilesLines
2022-06-17drm/i915/gt: Cleanup interface for MCR operationsMatt Roper1-18/+15
2022-06-17drm/i915/gt: Move multicast register handling to a dedicated fileMatt Roper1-1/+2
2022-06-02drm/i915/sseu: Disassociate internal subslice mask representation from uapiMatt Roper1-2/+2
2022-05-11drm/i915/pvc: read fuses for link copy enginesLucas De Marchi1-0/+29
2022-05-11drm/i915/pvc: Reset support for new copy enginesMatt Roper1-0/+8
2022-05-11drm/i915/pvc: Engine definitions for new copy enginesMatt Roper1-0/+56
2022-04-21Merge drm/drm-next into drm-intel-gt-nextRodrigo Vivi1-5/+6
2022-04-19drm/i915: Add Wa_22011802037 force cs haltTilak Tangudu1-0/+9
2022-04-11Merge drm/drm-next into drm-intel-nextJani Nikula1-32/+125
2022-03-22drm/i915/guc: Print the GuC error capture output register list.Alan Previn1-3/+1
2022-03-19drm/i915: Add logical mapping for video decode enginesMatthew Brost1-5/+17
2022-03-04drm/i915/xehp: Support platforms with CCS engines but no RCSMatt Roper1-0/+5
2022-03-02drm/i915: Use str_enabled_disabled()Lucas De Marchi1-1/+1
2022-03-02drm/i915: Use str_yes_no()Lucas De Marchi1-4/+5
2022-03-02drm/i915/xehp: handle fused off CCS enginesDaniele Ceraolo Spurio1-0/+25
2022-03-02drm/i915/xehp: Enable ccs/dual-ctx in RCU_MODEMatt Roper1-0/+17
2022-03-02drm/i915/xehp: Define context scheduling attributes in lrc descriptorMatt Roper1-1/+3
2022-03-02drm/i915: Move context descriptor fields to intel_lrc.hMatt Roper1-0/+1
2022-03-02drm/i915/xehp: CCS should use RCS setup functionsMatt Roper1-0/+6
2022-03-02drm/i915/xehp: CCS shares the render reset domainMatt Roper1-0/+4
2022-03-02drm/i915/xehp: Define compute class and engineMatt Roper1-0/+28
2022-02-25Merge drm/drm-next into drm-intel-gt-nextTvrtko Ursulin1-12/+4
2022-02-23Merge tag 'drm-intel-gt-next-2022-02-17' of git://anongit.freedesktop.org/drm...Rodrigo Vivi1-6/+3
2022-02-22drm/i915/gt: use get_reset_domain() helperTejas Upadhyay1-32/+42
2022-02-14drm/i915: move i915_cache_level_str() static in i915_debugfs.cJani Nikula1-11/+0
2022-02-11drm/i915: split out i915_gem_internal.h from i915_drv.hJani Nikula1-0/+1
2022-02-02drm/i915: Move GT registers to their own header fileMatt Roper1-0/+1
2022-01-31Merge drm/drm-next into drm-intel-nextRodrigo Vivi1-28/+40
2022-01-12drm/i915/gt: Move engine registers to their own headerMatt Roper1-0/+1
2022-01-11drm/i915: Use struct vma_resource instead of struct vma_snapshotThomas Hellström1-6/+3
2022-01-11drm/i915: Use the vma resource as argument for gtt binding / unbindingThomas Hellström1-2/+2
2022-01-10drm/i915: split out i915_cmd_parser.h from i915_drv.hJani Nikula1-1/+1
2021-12-09drm/i915/gt: Use hw_engine_masks as reset_domainsTejas Upadhyay1-0/+32
2021-12-01drm/i915: Update error capture code to avoid using the current vma stateThomas Hellström1-2/+6
2021-10-28drm/i915/pmu: Connect engine busyness stats from GuC to pmuUmesh Nerlige Ramappa1-27/+1
2021-10-28drm/i915/pmu: Add a name to the execlists statsUmesh Nerlige Ramappa1-6/+8
2021-10-15drm/i915/guc: Connect UAPI to GuC multi-lrc interfaceMatthew Brost1-3/+3
2021-10-15drm/i915: Add logical engine mappingMatthew Brost1-9/+51
2021-09-24drm/i915/gt: Register the migrate contexts with their enginesThomas Hellström1-0/+4
2021-09-21drm/i915/xehp: Check new fuse bits for SFC availabilityMatt Roper1-5/+20
2021-08-11drm/i915/dg2: Report INSTDONE_GEOM values in error stateMatt Roper1-0/+7
2021-08-11drm/i915/xehp: Loop over all gslices for INSTDONE processingMatt Roper1-22/+26
2021-07-29drm/i915/gt: remove GRAPHICS_VER == 10Lucas De Marchi1-3/+0
2021-07-28drm/i915/guc: Fix for error capture after full GPU reset with GuCJohn Harrison1-46/+94
2021-07-28drm/i915/guc: Capture error state on context resetMatthew Brost1-2/+9
2021-07-28drm/i915/guc: Direct all breadcrumbs for a class to single breadcrumbsMatthew Brost1-2/+26
2021-07-28drm/i915/guc: GuC virtual enginesMatthew Brost1-0/+14
2021-07-26drm/i915/gt: nuke gen6_hw_idLucas De Marchi1-6/+0
2021-07-24drm/i915/xehp: Extra media engines - Part 1 (engine definitions)John Harrison1-0/+44
2021-07-23drm/i915/xehp: VDBOX/VEBOX fusing registers are enable-basedTvrtko Ursulin1-1/+8
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