| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2022-05-27 | drm/i915/bios: Split VBT data into per-panel vs. global parts | Ville Syrjälä | 1 | -3/+0 |
| 2022-03-31 | drm/i915: Move intel_drrs_compute_config() into intel_dp.c | Ville Syrjälä | 1 | -54/+0 |
| 2022-03-31 | drm/i915: Nuke intel_drrs_init() | Ville Syrjälä | 1 | -24/+0 |
| 2022-03-31 | drm/i915: Put fixed modes directly onto the panel's fixed_modes list | Ville Syrjälä | 1 | -17/+5 |
| 2022-03-31 | drm/i915: Extract intel_edp_has_drrs() | Ville Syrjälä | 1 | -24/+0 |
| 2022-03-22 | drm/i915: s/enable/active/ for DRRS | Ville Syrjälä | 1 | -10/+12 |
| 2022-03-16 | drm/i915: Deal with bigjoiner vs. DRRS | Ville Syrjälä | 1 | -1/+15 |
| 2022-03-16 | drm/i915: Do DRRS disable/enable during pre/post_plane_update() | Ville Syrjälä | 1 | -36/+4 |
| 2022-03-16 | drm/i915: Schedule DRRS work from intel_drrs_enable() | Ville Syrjälä | 1 | -2/+8 |
| 2022-03-16 | drm/i915: Don't cancel/schedule drrs work if the pipe wasn't affected | Ville Syrjälä | 1 | -9/+8 |
| 2022-03-16 | drm/i915: Determine DRRS frontbuffer_bits ahead of time | Ville Syrjälä | 1 | -1/+10 |
| 2022-03-16 | drm/i915: Fix DRRS frontbuffer_bits handling | Ville Syrjälä | 1 | -2/+4 |
| 2022-03-16 | drm/i915: Put the downclock_mode check back into can_enable_drrs() | Ville Syrjälä | 1 | -3/+5 |
| 2022-03-15 | drm/i915: Implement static DRRS | Ville Syrjälä | 1 | -1/+1 |
| 2022-03-15 | drm/i915: Enable eDP DRRS on ilk/snb port A | Ville Syrjälä | 1 | -4/+4 |
| 2022-03-15 | drm/i915: Stash DRRS state under intel_crtc | Ville Syrjälä | 1 | -153/+100 |
| 2022-03-15 | drm/i915: Eliminate the intel_dp dependency from DRRS | Ville Syrjälä | 1 | -48/+32 |
| 2022-03-15 | drm/i915: Introduce intel_drrs_type_str() | Ville Syrjälä | 1 | -2/+17 |
| 2022-03-15 | drm/i915: Introduce intel_panel_drrs_type() | Ville Syrjälä | 1 | -7/+3 |
| 2022-03-15 | drm/i915: Introduce intel_panel_{fixed,downclock}_mode() | Ville Syrjälä | 1 | -4/+7 |
| 2022-03-15 | drm/i915: Nuke dev_priv->drrs.type | Ville Syrjälä | 1 | -6/+4 |
| 2022-03-10 | drm/i915: Rename PIPECONF refresh select bits | Ville Syrjälä | 1 | -2/+2 |
| 2022-03-10 | drm/i915: Clean up DRRS refresh rate enum | Ville Syrjälä | 1 | -24/+20 |
| 2022-03-10 | drm/i915: Polish drrs type enum | Ville Syrjälä | 1 | -5/+5 |
| 2022-03-10 | drm/i915: Program MSA timing delay on ilk/snb/ivb | Ville Syrjälä | 1 | -0/+3 |
| 2022-03-10 | drm/i915: Pimp DRRS debugs | Ville Syrjälä | 1 | -5/+13 |
| 2022-03-10 | drm/i915: Constify intel_drrs_init() args | Ville Syrjälä | 1 | -1/+1 |
| 2022-03-10 | drm/i915: Fix up some DRRS type checks | Ville Syrjälä | 1 | -2/+2 |
| 2022-02-01 | drm/i915: Clear DP M2/N2 when not doing DRRS | Ville Syrjälä | 1 | -1/+5 |
| 2022-02-01 | drm/i915: Extract can_enable_drrs() | Ville Syrjälä | 1 | -12/+19 |
| 2022-02-01 | drm/i915: Disable DRRS on IVB/HSW port != A | Ville Syrjälä | 1 | -0/+8 |
| 2022-02-01 | drm/i915: Pass crtc+cpu_transcoder to intel_cpu_transcoder_set_m_n() | Ville Syrjälä | 1 | -1/+4 |
| 2022-02-01 | drm/i915: Split intel_cpu_transcoder_set_m_n() into M1/N1 vs. M2/N2 variants | Ville Syrjälä | 1 | -3/+2 |
| 2022-02-01 | drm/i915: Nuke intel_dp_set_m_n() | Ville Syrjälä | 1 | -2/+3 |
| 2022-01-28 | drm/i915: Move drrs hardware bit frobbing to small helpers | Ville Syrjälä | 1 | -31/+36 |
| 2022-01-28 | drm/i915: s/gmch_{m,n}/data_{m,n}/ | Ville Syrjälä | 1 | -1/+1 |
| 2021-09-08 | drm/i915/display: Prepare DRRS for frontbuffer rendering drop | José Roberto de Souza | 1 | -0/+9 |
| 2021-09-08 | drm/i915/display: Share code between intel_drrs_flush and intel_drrs_invalidate | José Roberto de Souza | 1 | -50/+32 |
| 2021-09-08 | drm/i915/display: Some code improvements and code style fixes for DRRS | José Roberto de Souza | 1 | -38/+20 |
| 2021-08-30 | drm/i915/display: Renaming DRRS functions to intel_drrs_*() | José Roberto de Souza | 1 | -58/+45 |
| 2021-08-30 | drm/i915/display: Move DRRS code its own file | José Roberto de Souza | 1 | -0/+477 |
