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path: root/drivers/gpu/drm/amd/display/dc/dml2_0
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2026-04-17drm/amd/display: Move dml2_destroy to non-FPU compilation unitRafal Ostrowski3-12/+13
On PREEMPT_RT kernels, vfree() can sleep because spin_lock is converted to rt_mutex. dml2_destroy() calls vfree() while inside an FPU-guarded region (preempt_count=2), which is illegal. dml2_wrapper_fpu.c is compiled with CC_FLAGS_FPU which defines _LINUX_FPU_COMPILATION_UNIT, making DC_RUN_WITH_PREEMPTION_ENABLED() resolve to a no-op. This prevents the macro from cycling FPU context off/on around vfree(). Move dml2_destroy() to dml2_wrapper.c (non-FPU compilation unit) where DC_RUN_WITH_PREEMPTION_ENABLED() properly cycles DC_FP_END/ DC_FP_START around vfree(). This pairs it with dml2_allocate_memory() which already lives there. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: add pstate schedule admissibility flags and frame-time utilityWenjing Liu3-0/+14
[Why] Core needs to track pstate schedule admissibility for different global change scenarios (fclk, temp read, PPT) and requires a reusable way to compute per-stream frame time from timing parameters. [How] Extend dml2_core_internal_mode_support_info with: fclk_pstate_schedule_admissible temp_read_pstate_schedule_admissible ppt_pstate_schedule_admissible Add dummy_double_array[3][DML2_MAX_PLANES] to dml2_core_calcs_mode_support_locals. Introduce dml2_core_utils_get_frame_time_us() in dml2_core_utils.c and export it in dml2_core_utils.h to compute frame time in microseconds from stream timing (vline time * (vactive + vblank)). Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: add const qualifiers to watermark params structWenjing Liu1-17/+17
[why] There are few non const input pointer fields. Setting them to const to prevent future modification of read-only data. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: fix math_mod() using arg1 instead of arg2Wenjing Liu1-1/+1
[Why] math_mod() multiplied by arg1 instead of arg2, returning a wrong result for any non-trivial modulo operation. [How] Replace arg1 with arg2 in the subtraction term to correctly implement fmod(arg1, arg2). Cc: Mario Limonciello <mario.limonciello@amd.com> Cc: Alex Deucher <alexander.deucher@amd.com> Cc: stable@vger.kernel.org Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Remove Duplicate Prefetch ParameterZheng, Austin2-3/+0
[Why/How] UrgLatency value is passed in twice to the prefetch calculations. Once through the UrgentLatency term and once through the Turg term. Only Turg is used in the prefetch calculation so remove the unused UrgentLatency parameter Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Zheng, Austin <Austin.Zheng@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Add DCN42 PMO policy for DML2.1Nicholas Kazlauskas5-7/+229
[Why] The MinTTU policy in DML2.1 does not guarantee that we support p-state in blank. This is a delta vs dml2 and earlier revisions as the prefetch mode override has been removed in favor of a more configurable pstate optimizer. [How] Split off DCN42 with its own PMO helpers so that we can use a simpler strategy of only allowing the mode if we support p-state in vblank and if vactive has enough latency hiding. The actual hookup to use these helpers in the PMO factory will be done in a later patch to satisfy build system requirements. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: update dcn42 memory latenciesDmytro Laktyushkin1-3/+16
Add latency update based on memory type to dml2.1 Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Fix DCN42 gpuvm_min_page_size_kbytes in SOC BBNicholas Kazlauskas1-1/+1
[Why & How] To match the HW specification this should be 4, not 256. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Pass min page size from SOC BB to dml2_1 plane configNicholas Kazlauskas1-6/+15
[Why] Like dml2_0 this isn't guaranteed to be constant for every ASIC. This can cause corruption or underflow for linear surfaces due to a wrong PTE_ROW_HEIGHT_LINEAR value if not correctly specified. [How] Like dml2_0 pass in the SOC bb into the plane configuration population functions. Set both GPUVM and HostVM page sizes in the overrides. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Correct MALL parameters for DCN42 soc bbNicholas Kazlauskas1-1/+1
[Why & How] The MALL and DCC parameters were copied and pasted from a previous ASIC but the correct value per HW specification should all be 0. If not correct this can impact urgent bandwidth calculation and PMO. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Fix HostVMMinPageSize unit mismatch in DML2.1Nicholas Kazlauskas1-6/+6
[Why] This was found back on DML2 but was missed when creating DML2.1. The bottom layer calculation (CalculateHostVMDynamicLevels) expects a value in bytes, not KB, but we pass in the value in KB (eg. 4). This causes an extra page table level to be required in the prefetch bytes which can be significant overhead - preventing some modes from being supported that should otherwise be. [How] Correct the units by multiplying the input and override values by 1024. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: update dcn42 bounding boxCharlene Liu2-3/+3
[why] update according hw spec. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Charlene Liu <Charlene.Liu@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Drop unused tiling formats from dml2Roman Li3-78/+2
Remove unused legacy tiling format support from dml2. Legacy asics don't use dml2. Fixes: e56e3cff2a1b ("drm/amd/display: Sync dcn42 with DC 3.2.373") Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-04-17drm/amd/display: Fix unused parameters warnings in dml2_0Gaghik Khachatrian18-0/+94
[Why] Resolve warnings by marking unused parameters explicitly. [How] Keep parameter names in signatures and add a line with '(void)param;' inside the function body Preserved function signatures and avoids breaking code paths that may reference the parameter under conditional compilation. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Reviewed-by: Clayton King <clayton.king@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-30drm/amd/display: Silence type conversion warnings in dml2Gaghik Khachatrian7-19/+41
[Why] Compiler build generates type conversion warnings throughout dc/dml2_0 where values are implicitly narrowed (e.g. int/uint32_t/uint64_t assigned to uint8_t, unsigned char, char, bool, or dml_bool_t), cluttering build output and masking genuine issues. [How] Add explicit casts at each narrowing assignment with ASSERT guards to catch out-of-range values in debug builds: - uint8_t: otg_inst, num_planes, pipe_idx, vblank_index fields - unsigned char: pipe_dlg_param.otg_inst from tg->inst - char: mcache num_pipes from num_dpps_required - bool/dml_bool_t: INTERLACE bitfield and fams2 enable flag use != 0 - uint64_t: widen min_hardware_refresh_in_uhz to hold div64_u64 result, then cast to unsigned long for min_refresh_uhz with ASSERT Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-30drm/amd/display: Move FPU Guards From DML To DC - Part 3Rafal Ostrowski5-5/+9
[Why] FPU guards (DC_FP_START/DC_FP_END) are required to wrap around code that can manipulates floats. To do this properly, the FPU guards must be used in a file that is not compiled as a FPU unit. If the guards are used in a file that is a FPU unit, other sections in the file that aren't guarded may be end up being compiled to use FPU operations. [How] Added DC_FP_START and DC_FP_END to DC functions that call DML functions using FPU. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-30drm/amd/display: Move FPU Guards From DML To DC - Part 2Rafal Ostrowski7-471/+484
[Why] FPU guards (DC_FP_START/DC_FP_END) are required to wrap around code that can manipulates floats. To do this properly, the FPU guards must be used in a file that is not compiled as a FPU unit. If the guards are used in a file that is a FPU unit, other sections in the file that aren't guarded may be end up being compiled to use FPU operations. [How] Removed DC_FP_START and DC_FP_END. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Rafal Ostrowski <rafal.ostrowski@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chuanyu Tseng <Chuanyu.Tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-30drm/amd/display: using cm structure for lut3d related infoDillon Varone1-10/+16
[Why] Using the alternative implementation via cm structure of config lut3d data Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: ChuanYu Tseng <ChuanYu.Tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-30drm/amd/display: Fix silence signed/unsigned mismatch warnings in dmlClay King2-7/+7
[Why & How] Fix signed/unsigned mismatch warnings by using the same signedness for a given value Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Clay King <clayking@amd.com> Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-30drm/amd/display: Fix bounds checking in dml2_0 clock table arrayGabe Teeger3-6/+32
[Why] Multiple locations in dml2_0 used num_clk_values-1 as array index without checking if num_clk_values > 0. When num_clk_values is 0, this results in accessing array index -1, which wraps to 255 for unsigned types, causing out-of-bounds memory access and potential crashes. [How] Add proper bounds checking using ternary operators to guard all num_clk_values-1 array accesses. When num_clk_values is 0, return 0 as fallback value instead of accessing invalid memory. This prevents buffer overflows while maintaining backward compatibility and provides sensible default behavior for empty clock tables. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gabe Teeger <gabe.teeger@amd.com> Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-24drm/amd/display: clean up typecasts and constants in dcn4_calcsAdriano Vero1-16/+16
Signed-off-by: Adriano Vero <litaliano00.contact@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-23drm/amd/display: Rework YCbCr422 DSC policyRelja Vojvodic1-3/+3
- Reworked YCbCr4:2:2 Native/Simple policy decision making with DSC enabled based on DSC caps and stream signal type Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Relja Vojvodic <Relja.Vojvodic@amd.com> Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-23drm/amd/display: Fix Signed/Unsigned Int Usage Compiler WarningGaghik Khachatrian1-1/+1
[Why] Compiler generates compiler warnings when signed enum constants or literal -1 are implicitly converted to unsigned integer types, cluttering build output and masking genuine issues. [How] Use UINT_MAX as the invalid sentinel for unsigned IDs and align loop/index types to unsigned where appropriate to remove implicit signed-to-unsigned conversions, with no functional behavior change. Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-17drm/amd/display: Plumb MRQ programming out of DML for dml2_1Nicholas Kazlauskas1-0/+22
[Why] If the MRQ is present then these fields are also required to be plumbed out to the requestor for programming. [How] Pipe the fields out through rq_dlg_get_rq_reg. The implementation follows the previous generation in dml2_0 for DCN35 but adjusted for the new helpers and coding style of dml2_1. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-17drm/amd/display: Add dcn_mrq_present FieldAustin Zheng1-0/+1
[Why/How] Add MRQ flag so it can be passed from ip_caps to ip_params Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-17drm/amd/display: Fix number of oppAustin Zheng1-0/+1
[Why/How] Patch number of opp based on IP caps Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Chuanyu Tseng <chuanyu.tseng@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11drm/amd/display: Sync dcn42 with DC 3.2.373Roman Li21-230/+230
This patch provides a bulk merge to align driver support for DCN42 with Display Core version 3.2.373. It includes upgrade for: - clk_mgr - dml2/dml21 - optc - hubp - mpc - optc - hwseq Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11drm/amd/display: Add DML support for dcn42Roman Li13-0/+270
DML support for DCN 4.2 Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11drm/amd/display: Enable dcn42 DC clk_mgrRoman Li1-0/+359
Add support for DCN 4.2 clock manager. Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Roman Li <Roman.Li@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11drm/amd/display: Fix compile warnings in dml2_0Gaghik Khachatrian1-2/+2
Fix static analysis warnings by ensuring swath size temporaries are initialized before use. No functional change intended. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11drm/amd/display: Add min clock init for DML21 mode programmingOvidiu Bunea3-0/+27
[WHY & HOW] 0 stream cases do not go through any DML validation which leaves DCN clocks in unoptimized states. If requesting DML validation or programming with 0 streams, program DCN clocks to lowest DPM state. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Ovidiu Bunea <ovidiu.bunea@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-11drm/amd/display: Clean up NULL pointer warnings in dml2Gaghik Khachatrian1-3/+38
This commit addresses multiple warnings by adding defensive checks for NULL pointers before dereferencing them. The changes ensure that pointers such as are validated, preventing potential undefined behavior. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Gaghik Khachatrian <gaghik.khachatrian@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-03-03drm/amd/display: Silence unused variable warningClay King1-3/+3
[WHY & HOW] Remove unused dpp_pipe_count variable. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Clay King <clayking@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Add gpuvm and hvm params to dml21Dmytro Laktyushkin3-2/+9
[Why & How] Add missing params to display configuration for dml21 Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-23drm/amd/display: Refactor fams2 calculationsDillon Varone2-99/+107
[WHY&HOW] Cleanup calculations based on version to improve for future expansion. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-19Revert "drm/amd/display: Add Handling for gfxversion DcGfxBase"Nicholas Carbones1-3/+0
This reverts commit 2e193f5b1b4f ("drm/amd/display: Add Handling for gfxversion DcGfxBase") Reason for revert: Cause some regressions Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Carbones <Nicholas.Carbones@amd.com> Signed-off-by: Ray Wu <ray.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-12drm/amd/display: Fix the incorrect type in dml_printAlex Hung1-1/+1
[Why & How] soc->max_outstanding_reqs is a dml_uint_t, not a dml_float_t. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-04drm/amd/display: Add Handling for gfxversion DcGfxBaseNicholas Carbones1-0/+3
[Why] There is no way to set tiling in dml in the case that gfxversion is DcGfxBase. [How] Where tiling is updated based on Gfx, add case for DcGfxBase and set tiling to dml2_sw_linear. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Carbones <ncarbone@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-04drm/amd/display: Match expected data typesZheng Austin2-19/+19
[Why/How] Data types should match what is expected. Update/cast data accordingly. Also change ASSERT to use DML_ASSERT instead Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Zheng Austin <Austin.Zheng@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2026-02-04drm/amd/display: Add lpddr5 handling to dml2.1Dmytro Laktyushkin4-25/+64
[Why & How] Memory bandwidth calculations work differently than for ddr. Add lpddr5 handling. Reviewed-by: Charlene Liu <charlene.liu@amd.com> Signed-off-by: Dmytro Laktyushkin <dmytro.laktyushkin@amd.com> Signed-off-by: Wayne Lin <wayne.lin@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16drm/amd/display: Fix presentation of Z8 efficiencyAustin Zheng1-2/+3
[Why/How] Should differentiate when vblank is or isn't included Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Austin Zheng <Austin.Zheng@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-16drm/amd/display: Add use_max_lsw parameterOleh Kuzhylnyi2-0/+2
[WHY&HOW] Add use_max_lsw parameter to make prefetch for linear surfaces similar to tiled. Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Oleh Kuzhylnyi <okuzhyln@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amd/display: Additional info from DML for DMUNevenko Stupar2-1/+3
[WHAT] Add additional info from DML for DMU when applicable on future platforms. Reviewed-by: Alvin Lee <alvin.lee2@amd.com> Signed-off-by: Nevenko Stupar <Nevenko.Stupar@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amd/display: Refactor dml_core_mode_support to reduce stack frameAlex Hung1-63/+71
[WHAT] When compiling Linux kernel with clang, the following warning / error messages pops up: drivers/gpu/drm/amd/amdgpu/../dal-dev/dc/dml2_0/display_mode_core.c:6853:12: error: stack frame size (2120) exceeds limit (2056) in 'dml_core_mode_support' [-Werror,-Wframe-larger-than] 6853 | dml_bool_t dml_core_mode_support(struct display_mode_lib_st *mode_lib) [HOW] Refactoring CalculateVMRowAndSwath_params assignments to a new function helps reduce the stack frame size in dml_core_mode_support. Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4733 Reviewed-by: Austin Zheng <austin.zheng@amd.com> Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Chenyu Chen <chen-yu.chen@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amd/display: correct kernel-doc in dml21_wrapper.hRandy Dunlap1-3/+4
Fix all kernel-doc warnings in dml21_wrapper.h: - add missing @dml_ctx entries (2 places) - fix function prototype typo for dml21_create() - change a blank kernel-doc line to " *" Fixes these warnings: Warning: drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h:30 function parameter 'dml_ctx' not described in 'dml21_create' Warning: drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h:30 expecting prototype for dml2_create(). Prototype was for dml21_create() instead Warning: drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h:55 bad line: Warning: drivers/gpu/drm/amd/display/dc/dml2_0/dml21/dml21_wrapper.h:61 function parameter 'dml_ctx' not described in 'dml21_validate' Signed-off-by: Randy Dunlap <rdunlap@infradead.org> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amd/display: Drop FPU flags from dml21_wrapper.cHarry Wentland1-2/+0
[WHAT] The existing CFLAGS_ lines were pointing to a wrong location for dml21_wrapper.c and were thereby ineffective. This means dml21_wrapper.c is not an FPU compilation unit. Remove the (erroneous) CFLAGS_ entries. Reviewed-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amd/display: Move dml2_create and init to the non-FPU dml2_wrapperHarry Wentland4-77/+107
[WHAT] dml2_init calls DC_FP_START/END and needs to be moved out of the FPU compilation unit. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amd/display: Move dml2_validate to the non-FPU dml2_wrapperHarry Wentland4-32/+47
[WHAT] It calls DC_FP_START/END and shouldn't be living inside an FPU compilation unit. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-08drm/amd/display: Rename dml2_wrapper.c to dml2_wrapper_fpu.cHarry Wentland2-3/+3
[WHAT] This function is an FPU compilation unit. Therefore it's not allowed to call DC_FP_START/END functions. It currently does so and we'll need to move those functions out. Therefore rename the existing compilation unit so we can introduce a non-FPU dml2_wrapper.c. Reviewed-by: Austin Zheng <austin.zheng@amd.com> Signed-off-by: Harry Wentland <harry.wentland@amd.com> Signed-off-by: Alex Hung <alex.hung@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2025-12-02drm/amd/display: fix typo in display_mode_core_structs.hAditya Gollamudi1-1/+1
Fix a typo in a comment, change "enviroment" to "environment" in drivers/gpu/drm/amd/display/dc/dml2/display_mode_core_structs.h Fixes: e6a8a000cfe6 ("drm/amd/display: Rename dml2 to dml2_0 folder") Acked-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Aditya Gollamudi <adigollamudi@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Roman Li <roman.li@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
generated by cgit v1.2.3 (git 2.39.0) at 2026-05-14 07:00:43 +0300