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path: root/drivers/gpu/drm/amd/display/dc/dml/dcn303
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2025-08-27drm/amd/display: Array offset used before range checkClay King1-1/+1
Consolidating multiple CodeQL Fixes for alerts with rule id: cpp/offset-use-before-range-check Reviewed-by: Joshua Aberback <joshua.aberback@amd.com> Signed-off-by: Clay King <clayking@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-05-02drm/amd/display: Fix index may exceed array range within ↵Hersen Wu1-0/+10
fpu_update_bw_bounding_box [Why] Coverity reports OVERRUN warning. soc.num_states could be 40. But array range of bw_params->clk_table.entries is 8. [How] Assert if soc.num_states greater than 8. Reviewed-by: Alex Hung <alex.hung@amd.com> Acked-by: Tom Chung <chiahsuan.chung@amd.com> Signed-off-by: Hersen Wu <hersenxs.wu@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2024-01-16drm/amd/display: Ensure populate uclk in bb constructionAlvin Lee1-0/+11
[Description] - For some SKUs, the optimal DCFCLK for each UCLK is less than the smallest DCFCLK STA target due to low memory bandwidth. There is an assumption that the DCFCLK STA targets will always be less than one of the optimal DCFCLK values, but this is not true for SKUs that have low memory bandwidth. In this case we need to populate the optimal UCLK for each DCFCLK STA targets as the max UCLK freq. - Also fix a bug in DML where start_state is not assigned and used correctly. Reviewed-by: Samson Tam <samson.tam@amd.com> Reviewed-by: Chaitanya Dhere <chaitanya.dhere@amd.com> Acked-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Alvin Lee <alvin.lee2@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-07-28drm/amd/display: Clean up some inconsistent indentingJiapeng Chong1-9/+6
No functional modification involved. smatch warnings: drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:205 dcn303_fpu_update_bw_bounding_box() warn: inconsistent indenting. drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.c:355 dcn303_fpu_init_soc_bounding_box() warn: inconsistent indenting. Reported-by: Abaci Robot <abaci@linux.alibaba.com> Signed-off-by: Jiapeng Chong <jiapeng.chong@linux.alibaba.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2022-03-15drm/amd/display: move FPU associated DCN303 code to DML folderJasdeep Dhillon2-0/+394
[Why & How] As part of the FPU isolation work documented in https://patchwork.freedesktop.org/series/93042/, isolate code that uses FPU in DCN303 to DML, where all FPU code should locate. Co-authored-by: Jasdeep Dhillon <jasdeep.dhillon@amd.com> Reviewed-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Acked-by: Alan Liu <HaoPing.Liu@amd.com> Signed-off-by: Jasdeep Dhillon <jasdeep.dhillon@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>