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path: root/drivers/gpu/drm/amd/display/dc/dcn30
AgeCommit message (Expand)AuthorFilesLines
2021-05-11drm/amd/display: changing sr exit latencyMartin Leung1-1/+1
2021-03-25drm/amd/display: Correct algorithm for reversed gammaCalvin Hou1-8/+18
2021-03-04drm/amd/display: Remove Assert from dcn10_get_dig_frontendEric Bernstein1-0/+2
2020-10-27drm/amd/display: prevent null pointer accessDmytro Laktyushkin1-5/+7
2020-10-09drm/amd/display: Fix OPTC_DATA_FORMAT programmingDmytro Laktyushkin1-8/+0
2020-09-30drm/amd/display: add pipe reassignment prevention code to dcn3Dmytro Laktyushkin1-12/+49
2020-09-29amd/drm/display: avoid dcn3 on flip opp change for slave pipesDmytro Laktyushkin1-3/+40
2020-09-29drm/amd/display: Calc DLG from dummy p-state if full p-state unsupportedJoshua Aberback2-40/+79
2020-09-25drm/amdgpu/display: fix CFLAGS setup for DCN30Alex Deucher1-2/+16
2020-09-22drm/amd/display: eDP intermittent black screen during PnPPeikang Zhang1-0/+1
2020-09-16drm/amd/display: Remove duplicate includeChen Zhou1-1/+0
2020-09-16drm/amd/display: update dcn30_optc header with missing declarationsDmytro Laktyushkin2-3/+6
2020-09-16drm/amd/display: get socBB from VBIOSJun Lei1-0/+16
2020-09-16drm/amd/display: remove dc context from transfer functionJosip Pavic1-4/+0
2020-09-16drm/amd/display: adding pathway to retrieve stutter periodMartin Leung1-0/+3
2020-09-16drm/amd/display: Disable idle optimization when PSR is enabledZhan Liu1-14/+11
2020-09-16drm/amd/display: Enabling PSR on DCN30 on driver sideZhan Liu1-2/+16
2020-09-16drm/amd/display: Rename set_mst_bandwidth to align with DP specGeorge Shen1-2/+2
2020-09-16drm/amd/display: Triplebuffering should not be used by defaultAric Cyr1-0/+1
2020-09-16drm/amd/display: Compare mpcc_inst to mpcc_count instead of a constantJoshua Aberback1-3/+1
2020-08-26drm/amd/display: Add DPCS regs for dcn3 link encoderBhawanpreet Lakha1-0/+1
2020-08-19drm/amd/display: Add dsc_to_stream_resource for dcn3Bhawanpreet Lakha1-0/+1
2020-08-17drm/amd/display: Reset scrambling on Test PatternChris Park1-0/+1
2020-08-17drm/amd/display: Add read backlight interfaceYongqiang Sun1-1/+1
2020-08-17drm/amd/display: Assign correct left shiftChris Park1-1/+4
2020-08-11drm/amd/display: Disconnect pipe separetely when disable pipe splitAlvin Lee1-0/+2
2020-08-11drm/amd/display: Revert regressionAlvin Lee1-2/+0
2020-08-11drm/amd/display: Adjust static-ness of resource functionsJoshua Aberback2-12/+18
2020-08-05drm/amd/display: Constify dcn30_res_pool_funcsRikard Falkeborn1-1/+1
2020-08-05drm/amd/display: Separate pipe disconnect from rest of progrmamingAlvin Lee1-0/+2
2020-08-05drm/amd/display: Display goes blank after instIgor Kravchenko2-1/+54
2020-07-27drm/amd/display: Use proper abm/backlight functions for DCN3Bhawanpreet Lakha1-2/+3
2020-07-14drm/amd/display: Add missing DCN30 registers and fields for OTG_CRC_CNTL2Nicholas Kazlauskas1-0/+9
2020-07-14drm/amd/display: fix dcn3 p_state_change_support validation (v2)Dmytro Laktyushkin1-7/+39
2020-07-08drm/amd/display: Add missing reg mask for dcn3Bhawanpreet Lakha1-0/+1
2020-07-01drm/amd/display: enable seamless boot for dcn30Martin Leung2-127/+126
2020-07-01drm/amd/display: Update bounding box states (v2)Alvin Lee1-41/+22
2020-07-01drm/amd/display: Update DCN3 bounding boxAlvin Lee1-12/+102
2020-07-01drm/amd/display: Get num_chans from VBIOS tableAlvin Lee1-1/+6
2020-07-01drm/amd/display: Fix indenting in dcn30_set_output_transfer_func()Dan Carpenter1-3/+3
2020-07-01drm/amd/display: drop duplicated .dsc_pg_control for dcn30Flora Cui1-1/+0
2020-07-01drm/amd/display: drop duplicated structureFlora Cui1-57/+1
2020-07-01drm/amd/display: Add DCN3 blocks to MakefileBhawanpreet Lakha1-0/+54
2020-07-01drm/amd/display: fix and simplify pipe split logic for DCN3Dmytro Laktyushkin1-120/+93
2020-07-01drm/amd/display: Init function tables for DCN3Bhawanpreet Lakha2-0/+181
2020-07-01drm/amd/display: Add DCN3 VPGBhawanpreet Lakha2-0/+327
2020-07-01drm/amd/display: Add DCN3 AFMTBhawanpreet Lakha2-0/+436
2020-07-01drm/amd/display: Add DCN3 ResourceBhawanpreet Lakha2-0/+2780
2020-07-01drm/amd/display: Add DCN3 HWSEQBhawanpreet Lakha2-0/+784
2020-07-01drm/amd/display: Add DCN3 DWBBhawanpreet Lakha3-0/+1541
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