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path: root/drivers/gpu/drm/amd/display/dc/clk_mgr
AgeCommit message (Expand)AuthorFilesLines
2026-03-25drm/amd/display: Add pixel_clock to amd_pp_display_configurationTimur Kristóf1-1/+1
2025-08-28drm/amd/display: Don't overclock DCE 6 by 15%Timur Kristóf1-5/+3
2025-08-28drm/amd/display: Fill display clock and vblank time in dce110_fill_display_co...Timur Kristóf3-11/+3
2025-08-28drm/amd/display: Find first CRTC and its line time in dce110_fill_display_con...Timur Kristóf1-10/+20
2025-08-28drm/amd/display: Fix DP audio DTO1 clock source on DCE 6.Timur Kristóf1-15/+6
2025-08-28drm/amd/display: Don't overwrite dce60_clk_mgrTimur Kristóf1-1/+0
2025-06-04drm/amd/display: Guard against setting dispclk low for dcn31xJing Zhou2-11/+22
2025-02-21drm/amd/display: Add NULL pointer check for kzallocHersen Wu2-0/+16
2024-09-08drm/amd/display: Check num_valid_sets before accessing reader_wm_sets[]Alex Hung1-1/+2
2024-06-12drm/amd/display: Add dtbclk access to dcn315Swapnil Patel1-0/+8
2024-04-17drm/amd/display: fix disable otg wa logic in DCN316Fudongwang1-7/+12
2024-02-01drm/amd/display: Port DENTIST hang and TDR fixes to OTG disable W/ANicholas Kazlauskas1-12/+9
2024-01-20drm/amd/display: update dcn315 lpddr pstate latencyDmytro Laktyushkin1-4/+4
2023-09-13drm/amd/display: Add smu write msg id fail retry processFudong Wang1-4/+16
2023-08-03drm/amd/display: Keep PHY active for dp configAgustin Gutierrez1-0/+5
2023-07-27drm/amd/display: Keep PHY active for DP displays on DCN31Nicholas Kazlauskas1-0/+5
2023-07-19drm/amd/display: Add logging for display MALL refresh settingWesley Chalmers1-0/+3
2023-05-17drm/amd/display: Add Z8 allow states to z-state support listNicholas Kazlauskas2-4/+12
2023-05-17drm/amd/display: Fixes for dcn32_clk_mgr implementationAurabindo Pillai1-0/+5
2023-05-11drm/amd/display (gcc13): fix enum mismatchJiri Slaby (SUSE)1-1/+3
2023-03-30drm/amd/display: Update clock table to include highest clock settingSwapnil Patel1-1/+18
2023-03-10drm/amd: Avoid ASSERT for some message failuresMario Limonciello1-0/+3
2022-12-31drm/amd/display: Fix DTBCLK disable requests and SRC_SEL programmingAlvin Lee1-1/+1
2022-11-22drm/amd/display: Align dcn314_smu logging with other DCNsRoman Li1-2/+9
2022-11-10drm/amd/display: Update SR watermarks for DCN314Nicholas Kazlauskas1-16/+16
2022-11-02drm/amd/display: Set memclk levels to be at least 1 for dcn32Dillon Varone1-0/+3
2022-11-02drm/amd/display: Limit dcn32 to 1950Mhz display clockJun Lei1-4/+4
2022-10-11drm/amd/display: Fix bug preventing FCLK Pstate allow message being sentDillon Varone1-2/+2
2022-10-11drm/amd/display: Acquire FCLK DPM levels on DCN32Dillon Varone1-14/+27
2022-10-11drm/amd/display: increase hardware status wait timeVladimir Stempen1-2/+2
2022-10-11drm/amd/display: Update PMFW z-state interface for DCN314Nicholas Kazlauskas1-8/+3
2022-10-06drm/amd/display: Reorder FCLK P-state switch sequence for DCN32Dillon Varone1-21/+23
2022-09-29drm/amd/display: fill in clock values when DPM is not enabledSamson Tam1-0/+14
2022-09-29drm/amd/display: Wrap OTG disable workaround with FIFO controlNicholas Kazlauskas1-1/+10
2022-09-19drm/amd/display: Disable OTG WA for the plane_state NULL case on DCN314Nicholas Kazlauskas1-2/+1
2022-09-19drm/amd/display: increase dcn315 pstate change latencyDmytro Laktyushkin1-8/+14
2022-09-19drm/amd/display: Display distortion after hotplug 5K tiled displayMeenakshikumar Somasundaram4-20/+24
2022-09-19drm/amd/display: fix dcn315 memory channel count and width readDmytro Laktyushkin1-2/+1
2022-09-13drm/amd/display: Correct dram channel width for dcn314Duncan Ma1-0/+2
2022-08-25drm/amd/display: Adding log clock table from SMULeo Chen3-0/+140
2022-08-22drm/amd/display: remove unneeded semicolonYang Li1-1/+1
2022-08-17drm/amd/display: Unneeded semicolonmin tang1-1/+1
2022-08-17drm/amd/display: Update clock table policy for DCN314Nicholas Kazlauskas2-65/+154
2022-08-17drm/amd/display: Add debug parameter to retain default clock tableDaniel Miess1-1/+1
2022-08-10drm/amd/display: Correct DTBCLK for dcn314Duncan Ma2-12/+2
2022-08-10drm/amd/display: change family id name for DCN314Yifan Zhang1-2/+2
2022-08-10drm/amd/display: remove header from source fileMagali Lemes2-2/+2
2022-07-28drm/amd/display: Clean up some inconsistent indentingJiapeng Chong1-1/+2
2022-07-28drm/amd/display: Clean up some inconsistent indentingJiapeng Chong1-1/+2
2022-07-28drm/amd/display: Clean up some inconsistent indentingJiapeng Chong1-1/+2
generated by cgit v1.2.3 (git 2.39.0) at 2026-04-24 07:49:21 +0300