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path: root/drivers/gpu/drm/amd/amdgpu
AgeCommit message (Expand)AuthorFilesLines
4 daysdrm/amdgpu/vce1: Fix VCE 1 firmware size and offsetsTimur Kristóf1-4/+15
4 daysdrm/amdgpu/vce1: Check that the GPU address is < 128 MiBTimur Kristóf1-4/+8
4 daysdrm/amdgpu: Align amdgpu_gtt_mgr entries to TLB size on Tahiti (v2)Timur Kristóf1-1/+8
4 daysdrm/amdgpu/vpe: Force collaborate sync after TRAPAlan Liu1-1/+6
13 daysdrm/amdgpu/jpeg: set no_user_fence for JPEG v5.3.0 ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/jpeg: set no_user_fence for JPEG v5.0.1 ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/jpeg: set no_user_fence for JPEG v5.0.0 ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/jpeg: set no_user_fence for JPEG v4.0.5 ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/jpeg: set no_user_fence for JPEG v4.0.3 ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/jpeg: set no_user_fence for JPEG v4.0 ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/jpeg: set no_user_fence for JPEG v3.0 ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/jpeg: set no_user_fence for JPEG v2.5 ringYinjie Yao1-0/+2
13 daysdrm/amdgpu/jpeg: set no_user_fence for JPEG v2.0 ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/vcn: set no_user_fence for VCN v5.0.1 enc ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/vcn: set no_user_fence for VCN v5.0.0 enc ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/vcn: set no_user_fence for VCN v4.0.5 enc ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/vcn: set no_user_fence for VCN v4.0.3 enc ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/vcn: set no_user_fence for VCN v4.0 enc ringYinjie Yao1-0/+1
13 daysdrm/amdgpu/vcn: set no_user_fence for VCN v3.0 enc/dec ringsYinjie Yao1-0/+3
13 daysdrm/amdgpu/vcn: set no_user_fence for VCN v2.5 enc/dec ringsYinjie Yao1-0/+2
13 daysdrm/amdgpu/vcn: set no_user_fence for VCN v2.0 enc/dec ringsYinjie Yao1-0/+2
13 daysdrm/amd/display: properly handle family setting for early GC 11.5.4Alex Deucher1-3/+1
13 daysdrm/amdgpu: Only send RMA CPER when threshold is exceededKent Russell1-1/+1
13 daysdrm/amdgpu/gfx6: Support harvested SI chips with disabled TCCs (v2)Timur Kristóf1-0/+66
13 daysdrm/amdgpu/uvd3.1: Don't validate the firmware when already validatedTimur Kristóf1-0/+10
13 daysdrm/amdgpu: fix AMDGPU_INFO_READ_MMR_REGChristian König1-33/+24
13 daysdrm/amdgpu/gmc: Fix AMDGPU_GART_PLACEMENT_LOW to not overlap with VRAMTimur Kristóf1-1/+4
13 daysdrm/amdgpu: avoid double drm_exec_fini() in userq validateHongyan Xu1-1/+2
13 daysdrm/amdgpu/uvd4.2: Don't initialize UVD 4.2 when DPM is disabledTimur Kristóf1-0/+5
13 daysdrm/amdgpu/gfx11: look at the right prop for gfx queue priorityAlex Deucher1-1/+1
13 daysdrm/amdgpu/gfx10: look at the right prop for gfx queue priorityAlex Deucher1-1/+1
13 daysdrm/amdgpu: Remove dead negative offset check in amdgpu_virt_init_critical_re...Srinivasan Shanmugam1-5/+0
13 daysdrm/amdgpu: Drop redundant queue NULL check in hang detect workerSrinivasan Shanmugam1-1/+1
13 daysdrm/amdgpu: Add default case in DVI mode validationSrinivasan Shanmugam1-0/+2
13 daysdrm/amdgpu: GFX12.1 scratch memory limit up to 57-bitPhilip Yang2-3/+9
2026-05-17drm/amdgpu/vcn4: Avoid overflow on msg bound checkBenjamin Cheng1-1/+3
2026-05-17drm/amdgpu/vcn3: Avoid overflow on msg bound checkBenjamin Cheng1-1/+3
2026-05-17drm/amdgpu/sdma4: replace BUG_ON with WARN_ON in fence emissionJohn B. Moore1-2/+2
2026-05-17drm/amdgpu/gfx9: drop unnecessary 64-bit fence flag check in KIQJohn B. Moore1-3/+0
2026-05-17drm/amdgpu/userq: fix access to stale wptr mappingSunil Khatri1-58/+37
2026-05-17drm/amdgpu: zero-initialize GART table on allocationPhilip Yang1-3/+10
2026-05-17drm/amdgpu: Avoid reset in AMDGPU unload path for APUs with GFX V11 and higher.Shubhankar Milind Sardeshpande1-1/+5
2026-05-17drm/amdgpu/vcn3: Prevent OOB reads when parsing dec msgBenjamin Cheng1-4/+19
2026-05-17drm/amdgpu/vcn4: Prevent OOB reads when parsing dec msgBenjamin Cheng1-3/+18
2026-05-17drm/amdgpu/vce: Prevent partial address patchesBenjamin Cheng1-0/+3
2026-05-17drm/amdgpu/vcn4: Prevent OOB reads when parsing IBBenjamin Cheng1-11/+12
2026-05-17drm/amdgpu: Add bounds checking to ib_{get,set}_valueBenjamin Cheng1-4/+7
2026-05-17drm/amdgpu: gate VM CPU HDP flush on reset lockChenglei Xie1-1/+11
2026-05-17drm/amdgpu: Use SMUIO 15.0.0 offsets for TSC upper and lower count.Ramalingeswara Reddy, Kanala1-5/+26
2026-05-17drm/amdgpu: Use NBIF offset for register RCC_STRAP0_RCC_DEV0_EPF0_STRAP0 .Ramalingeswara Reddy, Kanala1-1/+8
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