Age | Commit message (Expand) | Author | Files | Lines |
2021-09-09 | Merge tag 'cxl-for-5.15' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl... | Linus Torvalds | 13 | -723/+988 |
2021-09-07 | cxl/registers: Fix Documentation warning | Dan Williams | 1 | -1/+14 |
2021-09-07 | cxl/pmem: Fix Documentation warning | Dan Williams | 1 | -2/+28 |
2021-09-07 | cxl/pci: Fix debug message in cxl_probe_regs() | Li Qiang (Johnny Li) | 1 | -2/+2 |
2021-09-07 | cxl/pci: Fix lockdown level | Dan Williams | 1 | -1/+1 |
2021-09-07 | cxl/acpi: Do not add DSDT disabled ACPI0016 host bridge ports | Alison Schofield | 1 | -4/+8 |
2021-08-11 | cxl/mem: Adjust ram/pmem range to represent DPA ranges | Ira Weiny | 1 | -8/+6 |
2021-08-10 | cxl/mem: Account for partitionable space in ram/pmem ranges | Ira Weiny | 2 | -5/+96 |
2021-08-07 | cxl/pci: Store memory capacity values | Ira Weiny | 2 | -3/+37 |
2021-08-06 | cxl/pci: Simplify register setup | Ben Widawsky | 3 | -27/+13 |
2021-08-06 | cxl/pci: Ignore unknown register block types | Ben Widawsky | 1 | -8/+12 |
2021-08-06 | cxl/core: Move memdev management to core | Ben Widawsky | 6 | -234/+275 |
2021-08-06 | cxl/pci: Introduce cdevm_file_operations | Dan Williams | 2 | -27/+53 |
2021-08-06 | cxl/core: Move register mapping infrastructure | Dan Williams | 3 | -228/+237 |
2021-08-06 | cxl/core: Move pmem functionality | Dan Williams | 4 | -202/+225 |
2021-08-06 | cxl/core: Improve CXL core kernel docs | Ben Widawsky | 1 | -2/+9 |
2021-08-06 | cxl: Move cxl_core to new directory | Ben Widawsky | 6 | -7/+10 |
2021-07-21 | bus: Make remove callback return void | Uwe Kleine-König | 1 | -2/+1 |
2021-06-18 | cxl/pci: Rename CXL REGLOC ID | Ben Widawsky | 2 | -2/+2 |
2021-06-18 | cxl/acpi: Use the ACPI CFMWS to create static decoder objects | Alison Schofield | 1 | -0/+122 |
2021-06-18 | cxl/acpi: Add the Host Bridge base address to CXL port objects | Alison Schofield | 1 | -5/+95 |
2021-06-16 | cxl/pmem: Register 'pmem' / cxl_nvdimm devices | Dan Williams | 5 | -16/+215 |
2021-06-16 | cxl/pmem: Add initial infrastructure for pmem support | Dan Williams | 6 | -2/+335 |
2021-06-16 | cxl/core: Add cxl-bus driver infrastructure | Dan Williams | 2 | -0/+95 |
2021-06-15 | cxl/pci: Add media provisioning required commands | Ben Widawsky | 1 | -0/+19 |
2021-06-12 | cxl/component_regs: Fix offset | Ben Widawsky | 1 | -1/+1 |
2021-06-12 | cxl/hdm: Fix decoder count calculation | Ben Widawsky | 2 | -1/+8 |
2021-06-10 | cxl/acpi: Introduce cxl_decoder objects | Dan Williams | 3 | -1/+347 |
2021-06-10 | cxl/acpi: Enumerate host bridge root ports | Dan Williams | 1 | -1/+92 |
2021-06-10 | cxl/acpi: Add downstream port data to cxl_port instances | Dan Williams | 3 | -4/+167 |
2021-06-10 | cxl/Kconfig: Default drivers to CONFIG_CXL_BUS | Dan Williams | 1 | -0/+2 |
2021-06-10 | cxl/acpi: Introduce the root of a cxl_port topology | Dan Williams | 5 | -0/+247 |
2021-06-06 | cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *' | Dan Williams | 1 | -7/+8 |
2021-06-06 | cxl/pci: Add HDM decoder capabilities | Ben Widawsky | 3 | -6/+166 |
2021-06-06 | cxl/pci: Reserve individual register block regions | Ira Weiny | 2 | -4/+34 |
2021-06-06 | cxl/pci: Map registers based on capabilities | Ira Weiny | 3 | -38/+180 |
2021-06-06 | cxl/pci: Reserve all device regions at once | Ira Weiny | 1 | -7/+11 |
2021-06-06 | cxl/pci: Introduce cxl_decode_register_block() | Ira Weiny | 1 | -8/+18 |
2021-05-26 | cxl/mem: Get rid of @cxlm.base | Ben Widawsky | 2 | -15/+11 |
2021-05-26 | cxl/mem: Move register locator logic into reg setup | Ben Widawsky | 1 | -67/+68 |
2021-05-26 | cxl/mem: Split creation from mapping in probe | Ben Widawsky | 1 | -24/+40 |
2021-05-26 | cxl/mem: Use dev instead of pdev->dev | Ben Widawsky | 1 | -1/+1 |
2021-05-26 | cxl/mem: Demarcate vendor specific capability IDs | Ben Widawsky | 1 | -1/+4 |
2021-05-26 | cxl/pci.c: Add a 'label_storage_size' attribute to the memdev | Vishal Verma | 2 | -0/+15 |
2021-05-26 | cxl: Rename mem to pci | Ben Widawsky | 3 | -16/+10 |
2021-05-15 | cxl/core: Refactor CXL register lookup for bridge reuse | Dan Williams | 3 | -44/+66 |
2021-05-15 | cxl/core: Rename bus.c to core.c | Dan Williams | 2 | -9/+10 |
2021-05-15 | cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devices | Dan Williams | 3 | -28/+61 |
2021-05-15 | cxl/mem: Move some definitions to mem.h | Dan Williams | 3 | -77/+82 |
2021-04-17 | cxl/mem: Fix memory device capacity probing | Dan Williams | 1 | -2/+5 |