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path: root/drivers/cxl
AgeCommit message (Expand)AuthorFilesLines
2021-06-18cxl/pci: Rename CXL REGLOC IDBen Widawsky2-2/+2
2021-06-18cxl/acpi: Use the ACPI CFMWS to create static decoder objectsAlison Schofield1-0/+122
2021-06-18cxl/acpi: Add the Host Bridge base address to CXL port objectsAlison Schofield1-5/+95
2021-06-16cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams5-16/+215
2021-06-16cxl/pmem: Add initial infrastructure for pmem supportDan Williams6-2/+335
2021-06-16cxl/core: Add cxl-bus driver infrastructureDan Williams2-0/+95
2021-06-15cxl/pci: Add media provisioning required commandsBen Widawsky1-0/+19
2021-06-12cxl/component_regs: Fix offsetBen Widawsky1-1/+1
2021-06-12cxl/hdm: Fix decoder count calculationBen Widawsky2-1/+8
2021-06-10cxl/acpi: Introduce cxl_decoder objectsDan Williams3-1/+347
2021-06-10cxl/acpi: Enumerate host bridge root portsDan Williams1-1/+92
2021-06-10cxl/acpi: Add downstream port data to cxl_port instancesDan Williams3-4/+167
2021-06-10cxl/Kconfig: Default drivers to CONFIG_CXL_BUSDan Williams1-0/+2
2021-06-10cxl/acpi: Introduce the root of a cxl_port topologyDan Williams5-0/+247
2021-06-06cxl/pci: Fixup devm_cxl_iomap_block() to take a 'struct device *'Dan Williams1-7/+8
2021-06-06cxl/pci: Add HDM decoder capabilitiesBen Widawsky3-6/+166
2021-06-06cxl/pci: Reserve individual register block regionsIra Weiny2-4/+34
2021-06-06cxl/pci: Map registers based on capabilitiesIra Weiny3-38/+180
2021-06-06cxl/pci: Reserve all device regions at onceIra Weiny1-7/+11
2021-06-06cxl/pci: Introduce cxl_decode_register_block()Ira Weiny1-8/+18
2021-05-26cxl/mem: Get rid of @cxlm.baseBen Widawsky2-15/+11
2021-05-26cxl/mem: Move register locator logic into reg setupBen Widawsky1-67/+68
2021-05-26cxl/mem: Split creation from mapping in probeBen Widawsky1-24/+40
2021-05-26cxl/mem: Use dev instead of pdev->devBen Widawsky1-1/+1
2021-05-26cxl/mem: Demarcate vendor specific capability IDsBen Widawsky1-1/+4
2021-05-26cxl/pci.c: Add a 'label_storage_size' attribute to the memdevVishal Verma2-0/+15
2021-05-26cxl: Rename mem to pciBen Widawsky3-16/+10
2021-05-15cxl/core: Refactor CXL register lookup for bridge reuseDan Williams3-44/+66
2021-05-15cxl/core: Rename bus.c to core.cDan Williams2-9/+10
2021-05-15cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams3-28/+61
2021-05-15cxl/mem: Move some definitions to mem.hDan Williams3-77/+82
2021-04-17cxl/mem: Fix memory device capacity probingDan Williams1-2/+5
2021-04-16cxl/mem: Fix register block offset calculationBen Widawsky1-1/+1
2021-04-06cxl/mem: Force array size of mem_commands[] to CXL_MEM_COMMAND_ID_MAXRobert Richter1-1/+1
2021-04-06cxl/mem: Disable cxl device power managementDan Williams1-0/+1
2021-04-06cxl/mem: Do not rely on device_add() side effects for dev_set_name() failuresDan Williams1-10/+29
2021-04-06cxl/mem: Fix synchronization mechanism for device removal vs ioctl operationsDan Williams1-47/+50
2021-04-06cxl/mem: Use sysfs_emit() for attribute show routinesDan Williams1-4/+4
2021-02-23cxl/mem: Fix potential memory leakBen Widawsky1-1/+3
2021-02-19cxl/mem: Return -EFAULT if copy_to_user() failsDan Carpenter1-1/+4
2021-02-17cxl/mem: Add set of informational commandsBen Widawsky1-0/+9
2021-02-17cxl/mem: Enable commands via CELBen Widawsky2-7/+218
2021-02-17cxl/mem: Add a "RAW" send commandBen Widawsky2-0/+150
2021-02-17cxl/mem: Add basic IOCTL interfaceBen Widawsky1-1/+282
2021-02-17cxl/mem: Register CXL memX devicesDan Williams4-2/+318
2021-02-17cxl/mem: Find device capabilitiesBen Widawsky3-2/+679
2021-02-17cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpointsDan Williams4-0/+118
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-28 20:48:47 +0300