Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2022-02-09 | cxl/pci: Rename pci.h to cxlpci.h | Dan Williams | 1 | -59/+0 |
2022-02-09 | cxl/acpi: Map component registers for Root Ports | Ben Widawsky | 1 | -0/+9 |
2022-02-09 | cxl/pci: Add new DVSEC definitions | Ben Widawsky | 1 | -0/+15 |
2022-02-09 | cxl: Flesh out register names | Ben Widawsky | 1 | -9/+10 |
2021-10-29 | cxl/pci: Convert register block identifiers to an enum | Ben Widawsky | 1 | -6/+8 |
2021-08-06 | cxl/pci: Simplify register setup | Ben Widawsky | 1 | -0/+1 |
2021-06-18 | cxl/pci: Rename CXL REGLOC ID | Ben Widawsky | 1 | -1/+1 |
2021-02-17 | cxl/mem: Find device capabilities | Ben Widawsky | 1 | -0/+14 |
2021-02-17 | cxl/mem: Introduce a driver for CXL-2.0-Type-3 endpoints | Dan Williams | 1 | -0/+17 |