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path: root/drivers/cxl/pci.c
AgeCommit message (Expand)AuthorFilesLines
2022-04-08cxl/pci: Drop shadowed variableDan Williams1-1/+0
2022-02-09cxl/pci: Emit device serial numberDan Williams1-0/+1
2022-02-09cxl/pci: Implement wait for media activeBen Widawsky1-1/+48
2022-02-09cxl/pci: Retrieve CXL DVSEC memory infoBen Widawsky1-0/+119
2022-02-09cxl/pci: Cache device DVSEC offsetBen Widawsky1-0/+6
2022-02-09cxl/pci: Store component register base in cxldsBen Widawsky1-0/+11
2022-02-09cxl/pci: Rename pci.h to cxlpci.hDan Williams1-1/+1
2022-02-09cxl/acpi: Map component registers for Root PortsBen Widawsky1-52/+0
2022-02-09cxl: Flesh out register namesBen Widawsky1-7/+7
2022-02-09cxl/pci: Defer mailbox status checks to command timeoutsDan Williams1-101/+33
2022-02-09cxl/pci: Implement Interface Ready TimeoutBen Widawsky1-0/+35
2021-11-15cxl/memdev: Change cxl_mem to a more descriptive nameIra Weiny1-60/+60
2021-10-29cxl/pci: Use pci core's DVSEC functionalityBen Widawsky1-24/+2
2021-10-29cxl/pci: Split cxl_pci_setup_regs()Ben Widawsky1-36/+37
2021-10-29cxl/pci: Add @base to cxl_register_mapDan Williams1-15/+16
2021-10-29cxl/pci: Make more use of cxl_register_mapBen Widawsky1-34/+25
2021-10-29cxl/pci: Remove pci request/release regionsBen Widawsky1-5/+0
2021-10-29cxl/pci: Fix NULL vs ERR_PTR confusionDan Williams1-1/+1
2021-10-29cxl/pci: Remove dev_dbg for unknown register blocksBen Widawsky1-3/+0
2021-09-22cxl/pci: Disambiguate cxl_pci further from cxl_memBen Widawsky1-33/+35
2021-09-21cxl/pci: Use module_pci_driverDan Williams1-22/+8
2021-09-21cxl/mbox: Move mailbox and other non-PCI specific infrastructure to the coreDan Williams1-922/+2
2021-09-21cxl/pci: Drop idr.hDan Williams1-1/+0
2021-09-21cxl/mbox: Introduce the mbox_send operationDan Williams1-55/+21
2021-09-21cxl/pci: Clean up cxl_mem_get_partition_info()Dan Williams1-24/+11
2021-09-21cxl/pci: Make 'struct cxl_mem' device type genericDan Williams1-40/+35
2021-09-07cxl/pci: Fix debug message in cxl_probe_regs()Li Qiang (Johnny Li)1-2/+2
2021-09-07cxl/pci: Fix lockdown levelDan Williams1-1/+1
2021-08-11cxl/mem: Adjust ram/pmem range to represent DPA rangesIra Weiny1-8/+6
2021-08-10cxl/mem: Account for partitionable space in ram/pmem rangesIra Weiny1-5/+91
2021-08-07cxl/pci: Store memory capacity valuesIra Weiny1-3/+33
2021-08-06cxl/pci: Simplify register setupBen Widawsky1-26/+12
2021-08-06cxl/pci: Ignore unknown register block typesBen Widawsky1-8/+12
2021-08-06cxl/core: Move memdev management to coreBen Widawsky1-227/+1
2021-08-06cxl/pci: Introduce cdevm_file_operationsDan Williams1-27/+38
2021-08-06cxl: Move cxl_core to new directoryBen Widawsky1-1/+1
2021-06-18cxl/pci: Rename CXL REGLOC IDBen Widawsky1-1/+1
2021-06-16cxl/pmem: Register 'pmem' / cxl_nvdimm devicesDan Williams1-6/+17
2021-06-15cxl/pci: Add media provisioning required commandsBen Widawsky1-0/+19
2021-06-06cxl/pci: Add HDM decoder capabilitiesBen Widawsky1-0/+15
2021-06-06cxl/pci: Reserve individual register block regionsIra Weiny1-0/+2
2021-06-06cxl/pci: Map registers based on capabilitiesIra Weiny1-21/+90
2021-06-06cxl/pci: Reserve all device regions at onceIra Weiny1-7/+11
2021-06-06cxl/pci: Introduce cxl_decode_register_block()Ira Weiny1-8/+18
2021-05-26cxl/mem: Get rid of @cxlm.baseBen Widawsky1-13/+11
2021-05-26cxl/mem: Move register locator logic into reg setupBen Widawsky1-67/+68
2021-05-26cxl/mem: Split creation from mapping in probeBen Widawsky1-24/+40
2021-05-26cxl/mem: Use dev instead of pdev->devBen Widawsky1-1/+1
2021-05-26cxl/pci.c: Add a 'label_storage_size' attribute to the memdevVishal Verma1-0/+12
2021-05-26cxl: Rename mem to pciBen Widawsky1-0/+1524
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-02 23:29:53 +0300