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path: root/drivers/cxl/mem.c
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2024-07-28Merge tag 'cxl-for-6.11' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-0/+1
2024-07-02cxl: add missing MODULE_DESCRIPTION() macrosJeff Johnson1-0/+1
2024-06-19cxl/mem: Fix no cxl_nvd during pmem region auto-assemblingLi Ming1-8/+9
2024-02-17cxl: Fix sysfs export of qos_class for memdevDave Jiang1-36/+0
2024-02-17cxl: Change 'struct cxl_memdev_state' *_perf_list to single 'struct cxl_dpa_p...Dave Jiang1-24/+4
2023-12-23cxl: Export sysfs attributes for memory device QoS classDave Jiang1-6/+61
2023-10-28cxl/pci: Add RCH downstream port AER register discoveryRobert Richter1-0/+2
2023-10-28cxl/hdm: Use stored Component Register mappings to map HDM decoder capabilityRobert Richter1-3/+2
2023-06-26Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-13/+3
2023-06-26cxl/mbox: Move mailbox related driver state to its own data structureDan Williams1-3/+7
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter1-9/+0
2023-06-25cxl/mem: Prepare for early RCH dport component register setupRobert Richter1-5/+4
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-1/+1
2023-06-25cxl/acpi: Probe RCRB later during RCH downstream port creationRobert Richter1-2/+2
2023-05-19cxl: Move cxl_await_media_ready() to before capacity info retrievalDave Jiang1-0/+3
2023-04-23cxl/mem: Add debugfs attributes for poison inject and clearAlison Schofield1-0/+28
2023-04-23cxl/memdev: Add trigger_poison_list sysfs attributeAlison Schofield1-0/+43
2022-12-05cxl/port: Add RCD endpoint port enumerationDan Williams1-8/+25
2022-12-05cxl/mem: Move devm_cxl_add_endpoint() from cxl_core to cxl_memDan Williams1-0/+38
2022-12-03cxl/pmem: Refactor nvdimm device registration, delete the workqueueDan Williams1-0/+9
2022-07-22cxl/mem: Enumerate port targets before adding endpointsDan Williams1-29/+1
2022-07-22cxl/port: Record parent dport when adding portsDan Williams1-4/+6
2022-07-10cxl/mem: Add a debugfs version of 'iomem' for DPA, 'dpamem'Dan Williams1-0/+23
2022-06-22cxl: Fix cleanup of port devices on failure to probe driver.Jonathan Cameron1-1/+6
2022-05-19cxl/port: Move endpoint HDM Decoder Capability init to port driverDan Williams1-11/+0
2022-05-19cxl/pci: Drop @info argument to cxl_hdm_decode_init()Dan Williams1-2/+1
2022-05-19cxl/mem: Merge cxl_dvsec_ranges() and cxl_hdm_decode_init()Dan Williams1-79/+1
2022-05-19cxl/mem: Skip range enumeration if mem_enable clearDan Williams1-1/+1
2022-05-19cxl/mem: Consolidate CXL DVSEC Range enumeration in the coreDan Williams1-6/+8
2022-05-19cxl/pci: Move cxl_await_media_ready() to the coreDan Williams1-1/+1
2022-05-19cxl/mem: Validate port connectivity before dvsec rangesDan Williams1-16/+16
2022-05-19cxl/mem: Fix cxl_mem_probe() error exitDan Williams1-2/+4
2022-05-19cxl/pci: Consolidate wait_for_media() and wait_for_media_ready()Dan Williams1-18/+1
2022-05-19cxl/mem: Drop mem_enabled check from wait_for_media()Dan Williams1-4/+0
2022-04-29cxl: Drop cxl_device_lock()Dan Williams1-2/+2
2022-04-23PM: CXL: Disable suspendDan Williams1-1/+21
2022-04-13cxl/mem: Replace redundant debug message with a commentDan Williams1-4/+10
2022-04-13cxl/mem: Rename cxl_dvsec_decode_init() to cxl_hdm_decode_init()Dan Williams1-6/+6
2022-04-13cxl/mem: Make cxl_dvsec_range() init failure fatalDan Williams1-0/+3
2022-04-13cxl/mem: Drop DVSEC vs EFI Memory Map sanity checkDan Williams1-23/+1
2022-02-09cxl/mem: Add the cxl_mem driverBen Widawsky1-0/+228
2021-05-26cxl: Rename mem to pciBen Widawsky1-1525/+0
2021-05-15cxl/core: Refactor CXL register lookup for bridge reuseDan Williams1-44/+6
2021-05-15cxl/mem: Introduce 'struct cxl_regs' for "composable" CXL devicesDan Williams1-20/+24
2021-05-15cxl/mem: Move some definitions to mem.hDan Williams1-20/+1
2021-04-17cxl/mem: Fix memory device capacity probingDan Williams1-2/+5
2021-04-16cxl/mem: Fix register block offset calculationBen Widawsky1-1/+1
2021-04-06cxl/mem: Force array size of mem_commands[] to CXL_MEM_COMMAND_ID_MAXRobert Richter1-1/+1
2021-04-06cxl/mem: Disable cxl device power managementDan Williams1-0/+1
2021-04-06cxl/mem: Do not rely on device_add() side effects for dev_set_name() failuresDan Williams1-10/+29
generated by cgit v1.2.3 (git 2.39.0) at 2024-11-18 22:41:57 +0300