summaryrefslogtreecommitdiff
path: root/drivers/cxl/core/port.c
AgeCommit message (Expand)AuthorFilesLines
2024-04-29cxl: Fix cxl_endpoint_get_perf_coordinate() support for RCHDave Jiang1-1/+14
2024-04-08cxl: Add checks to access_coordinate calculation to fail missing dataDave Jiang1-1/+18
2024-04-08cxl: Consolidate dport access_coordinate ->hb_coord and ->sw_coord into ->coordDave Jiang1-11/+37
2024-04-08cxl: Fix incorrect region perf data calculationDave Jiang1-32/+4
2024-04-08cxl: Fix retrieving of access_coordinates in PCIe pathDave Jiang1-13/+22
2024-04-05cxl: Remove checking of iter in cxl_endpoint_get_perf_coordinates()Dave Jiang1-1/+1
2024-03-13Merge branch 'for-6.9/cxl-einj' into for-6.9/cxlDan Williams1-0/+41
2024-03-13cxl/core: Add CXL EINJ debugfs filesBen Cheatham1-0/+41
2024-03-12cxl: Set cxlmd->endpoint before adding port deviceDave Jiang1-1/+1
2024-03-12cxl: Split out host bridge access coordinatesDave Jiang1-3/+32
2024-03-12cxl: Split out combine_coordinates() for common shared usageDave Jiang1-16/+2
2024-03-12ACPI: HMAT / cxl: Add retrieval of generic port coordinates for both access c...Dave Jiang1-1/+1
2024-01-06Merge branch 'for-6.7/cxl' into for-6.8/cxlDan Williams1-16/+8
2024-01-06cxl: Convert find_cxl_root() to return a 'struct cxl_root *'Dave Jiang1-2/+2
2024-01-06cxl: Introduce put_cxl_root() helperDave Jiang1-0/+9
2024-01-05cxl/port: Fix missing target list lockDan Williams1-15/+7
2024-01-05cxl/port: Fix decoder initialization when nr_targets > interleave_waysHuang Ying1-1/+1
2023-12-23cxl: Add helper function that calculate performance data for downstream portsDave Jiang1-0/+75
2023-12-23cxl: Calculate and store PCI link latency for the downstream portsDave Jiang1-0/+6
2023-12-23cxl: Add support for _DSM Function for retrieving QTG IDDave Jiang1-10/+39
2023-12-08cxl/hdm: Fix dpa translation lockingDan Williams1-2/+2
2023-10-31Merge branch 'for-6.7/cxl-commited' into cxl/nextDan Williams1-0/+32
2023-10-31Merge branch 'for-6.7/cxl' into cxl/nextDan Williams1-1/+5
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams1-0/+11
2023-10-31Merge branch 'for-6.7/cxl-rch-eh' into cxl/nextDan Williams1-45/+84
2023-10-28cxl: Export QTG ids from CFMWS to sysfs as qos_class attributeDave Jiang1-0/+11
2023-10-28cxl: Add decoders_committed sysfs attribute to cxl_portDave Jiang1-0/+25
2023-10-28cxl: Add cxl_decoders_committed() helperDave Jiang1-0/+7
2023-10-28PCI/AER: Refactor cper_print_aer() for use by CXL driver moduleTerry Bowman1-0/+1
2023-10-28cxl/port: Remove Component Register base address from struct cxl_portRobert Richter1-3/+1
2023-10-28cxl/hdm: Use stored Component Register mappings to map HDM decoder capabilityRobert Richter1-7/+22
2023-10-28cxl/port: Pre-initialize component register mappingsRobert Richter1-5/+7
2023-10-28cxl/port: Rename @comp_map to @reg_map in struct cxl_register_mapRobert Richter1-3/+3
2023-10-28cxl/port: Fix @host confusion in cxl_dport_setup_regs()Dan Williams1-12/+31
2023-10-28cxl/core/regs: Rename @dev to @host in struct cxl_register_mapRobert Richter1-2/+2
2023-10-28cxl/port: Fix delete_endpoint() vs parent unregistration raceDan Williams1-15/+19
2023-10-06cxl/memdev: Fix sanitize vs decoder setup lockingDan Williams1-0/+6
2023-09-23cxl/port: Fix cxl_test register enumeration regressionDan Williams1-4/+9
2023-09-16cxl/port: Quiet warning messages from the cxl_test environmentDan Williams1-1/+6
2023-06-26Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-45/+105
2023-06-26Merge branch 'for-6.5/cxl-perf' into for-6.5/cxlDan Williams1-0/+2
2023-06-26cxl/memdev: Formalize endpoint port linkageDan Williams1-2/+3
2023-06-26cxl/port: Rename CXL_DECODER_{EXPANDER, ACCELERATOR} => {HOSTONLYMEM, DEVMEM}Dan Williams1-3/+3
2023-06-25cxl/port: Store the downstream port's Component Register mappings in struct c...Robert Richter1-0/+11
2023-06-25cxl/port: Store the port's Component Register mappings in struct cxl_portRobert Richter1-0/+27
2023-06-25cxl/pci: Early setup RCH dport component registers from RCRBRobert Richter1-0/+7
2023-06-25cxl/port: Remove Component Register base address from struct cxl_dportRobert Richter1-1/+0
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-28/+33
2023-06-25cxl: Rename member @dport of struct cxl_dport to @dport_devRobert Richter1-10/+10
2023-06-25cxl/rch: Prepare for caching the MMIO mapped PCIe AER capabilityDan Williams1-2/+2
generated by cgit v1.2.3 (git 2.39.0) at 2025-03-15 06:22:31 +0300