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path: root/drivers/cxl/core/pci.c
AgeCommit message (Expand)AuthorFilesLines
2025-11-03cxl/port: Remove devm_cxl_port_enumerate_dports()Li Ming1-79/+8
2025-09-18cxl/test: Add mock version of devm_cxl_add_dport_by_dev()Dave Jiang1-3/+4
2025-09-18cxl: Defer dport allocation for switch portsDave Jiang1-0/+46
2025-09-18cxl/test: Refactor decoder setup to reduce cxl_test burdenDave Jiang1-0/+42
2025-05-09cxl/pci: Add comments to cxl_hdm_decode_init()Robert Richter1-9/+22
2025-05-09cxl/pci: Moving code in cxl_hdm_decode_init()Robert Richter1-8/+8
2025-05-09cxl: Remove else after returnRobert Richter1-1/+2
2025-04-09cxl/pci: Drop the parameter is_port of cxl_gpf_get_dvsec()Li Ming1-3/+9
2025-04-09cxl/pci: Update Port GPF timeout only when the first EP attachingLi Ming1-6/+4
2025-04-09cxl/core: Fix caching dport GPF DVSEC issueLi Ming1-8/+8
2025-03-15cxl/pci: Introduce cxl_gpf_get_dvsec()Davidlohr Bueso1-10/+20
2025-03-15cxl/pci: Support Global Persistent Flush (GPF)Davidlohr Bueso1-0/+87
2025-01-29Merge tag 'cxl-for-6.14' of git://git.kernel.org/pub/scm/linux/kernel/git/cxl...Linus Torvalds1-3/+3
2025-01-03driver core: Constify API device_find_child() and adapt for various usagesZijun Hu1-2/+2
2025-01-02cxl/pci: Add CXL Type 1/2 support to cxl_dvsec_rr_decode()Alejandro Lucero1-3/+3
2024-12-02module: Convert symbol namespace to string literalPeter Zijlstra1-9/+9
2024-09-23cxl: Calculate region bandwidth of targets with shared upstream linkDave Jiang1-0/+23
2024-09-09cxl/pci: simplify the check of mem_enabled in cxl_hdm_decode_init()Yanfei Xu1-10/+11
2024-09-09cxl/pci: Check Mem_info_valid bit for each applicable DVSECYanfei Xu1-4/+4
2024-09-09cxl/pci: Remove duplicated implementation of waiting for memory_info_validYanfei Xu1-36/+5
2024-09-09cxl/pci: Fix to record only non-zero rangesYanfei Xu1-7/+1
2024-09-04cxl/pci: Remove duplicate host_bridge->native_aer checkingLi Ming1-11/+6
2024-09-04cxl/pci: cxl_dport_map_rch_aer() cleanupLi Ming1-20/+13
2024-09-04cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()Li Ming1-4/+9
2024-09-04cxl/port: Use __free() to drop put_device() for cxl_portLi Ming1-4/+2
2024-08-10cxl/pci: Get AER capability address from RCRB only for RCH dportLi Ming1-4/+6
2024-07-17cxl/core/pci: Move reading of control register to immediately before usageForyun Ma1-4/+4
2024-05-08cxl: Add post-reset warning if reset results in loss of previously committed ...Dave Jiang1-0/+29
2024-05-08PCI/CXL: Move CXL Vendor ID to pci_ids.hDave Jiang1-3/+3
2024-03-13lib/firmware_table: Provide buffer length argument to cdat_table_parse()Robert Richter1-1/+7
2024-03-13cxl/pci: Get rid of pointer arithmetic reading CDAT tableRobert Richter1-36/+41
2024-03-13cxl/pci: Rename DOE mailbox handle to doe_mbRobert Richter1-10/+10
2024-02-17cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS windowRobert Richter1-3/+3
2024-01-29cxl/pci: Skip to handle RAS errors if CXL.mem device is detachedLi Ming1-12/+31
2023-12-23cxl: Calculate and store PCI link latency for the downstream portsDave Jiang1-0/+36
2023-12-09cxl/cdat: Free correct buffer on checksum errorIra Weiny1-7/+6
2023-11-03cxl/pci: Change CXL AER support check to use native AERTerry Bowman1-2/+2
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams1-12/+40
2023-10-28cxl: Add support for reading CXL switch CDAT tableDave Jiang1-5/+17
2023-10-28cxl: Add checksum verification to CDAT from CXLDave Jiang1-7/+23
2023-10-28cxl/pci: Disable root port interrupts in RCH modeTerry Bowman1-0/+32
2023-10-28cxl/pci: Add RCH downstream port error loggingTerry Bowman1-0/+96
2023-10-28cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman1-0/+36
2023-10-28cxl/pci: Update CXL error logging to use RAS register addressTerry Bowman1-13/+31
2023-10-28cxl/pci: Add RCH downstream port AER register discoveryRobert Richter1-0/+15
2023-06-26Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-2/+2
2023-06-26Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams1-23/+4
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-2/+2
2023-05-19cxl: Wait Memory_Info_Valid before access memory related infoDave Jiang1-9/+76
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams1-4/+23
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