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path: root/drivers/cxl/core/pci.c
AgeCommit message (Expand)AuthorFilesLines
2024-09-23cxl: Calculate region bandwidth of targets with shared upstream linkDave Jiang1-0/+23
2024-09-09cxl/pci: simplify the check of mem_enabled in cxl_hdm_decode_init()Yanfei Xu1-10/+11
2024-09-09cxl/pci: Check Mem_info_valid bit for each applicable DVSECYanfei Xu1-4/+4
2024-09-09cxl/pci: Remove duplicated implementation of waiting for memory_info_validYanfei Xu1-36/+5
2024-09-09cxl/pci: Fix to record only non-zero rangesYanfei Xu1-7/+1
2024-09-04cxl/pci: Remove duplicate host_bridge->native_aer checkingLi Ming1-11/+6
2024-09-04cxl/pci: cxl_dport_map_rch_aer() cleanupLi Ming1-20/+13
2024-09-04cxl/pci: Rename cxl_setup_parent_dport() and cxl_dport_map_regs()Li Ming1-4/+9
2024-09-04cxl/port: Use __free() to drop put_device() for cxl_portLi Ming1-4/+2
2024-08-10cxl/pci: Get AER capability address from RCRB only for RCH dportLi Ming1-4/+6
2024-07-17cxl/core/pci: Move reading of control register to immediately before usageForyun Ma1-4/+4
2024-05-08cxl: Add post-reset warning if reset results in loss of previously committed ...Dave Jiang1-0/+29
2024-05-08PCI/CXL: Move CXL Vendor ID to pci_ids.hDave Jiang1-3/+3
2024-03-13lib/firmware_table: Provide buffer length argument to cdat_table_parse()Robert Richter1-1/+7
2024-03-13cxl/pci: Get rid of pointer arithmetic reading CDAT tableRobert Richter1-36/+41
2024-03-13cxl/pci: Rename DOE mailbox handle to doe_mbRobert Richter1-10/+10
2024-02-17cxl/pci: Fix disabling memory if DVSEC CXL Range does not match a CFMWS windowRobert Richter1-3/+3
2024-01-29cxl/pci: Skip to handle RAS errors if CXL.mem device is detachedLi Ming1-12/+31
2023-12-23cxl: Calculate and store PCI link latency for the downstream portsDave Jiang1-0/+36
2023-12-09cxl/cdat: Free correct buffer on checksum errorIra Weiny1-7/+6
2023-11-03cxl/pci: Change CXL AER support check to use native AERTerry Bowman1-2/+2
2023-10-31Merge branch 'for-6.7/cxl-qtg' into cxl/nextDan Williams1-12/+40
2023-10-28cxl: Add support for reading CXL switch CDAT tableDave Jiang1-5/+17
2023-10-28cxl: Add checksum verification to CDAT from CXLDave Jiang1-7/+23
2023-10-28cxl/pci: Disable root port interrupts in RCH modeTerry Bowman1-0/+32
2023-10-28cxl/pci: Add RCH downstream port error loggingTerry Bowman1-0/+96
2023-10-28cxl/pci: Map RCH downstream AER registers for logging protocol errorsTerry Bowman1-0/+36
2023-10-28cxl/pci: Update CXL error logging to use RAS register addressTerry Bowman1-13/+31
2023-10-28cxl/pci: Add RCH downstream port AER register discoveryRobert Richter1-0/+15
2023-06-26Merge branch 'for-6.5/cxl-rch-eh' into for-6.5/cxlDan Williams1-2/+2
2023-06-26Revert "cxl/port: Enable the HDM decoder capability for switch ports"Dan Williams1-23/+4
2023-06-25cxl: Rename 'uport' to 'uport_dev'Dan Williams1-2/+2
2023-05-19cxl: Wait Memory_Info_Valid before access memory related infoDave Jiang1-9/+76
2023-05-18cxl/port: Enable the HDM decoder capability for switch portsDan Williams1-4/+23
2023-05-13cxl: Add missing return to cdat read error pathDave Jiang1-0/+1
2023-04-23cxl/port: Fix port to pci device assumptions in read_cdat_data()Dan Williams1-6/+7
2023-04-18cxl/pci: Rightsize CDAT response allocationLukas Wunner1-17/+19
2023-04-18cxl/pci: Simplify CDAT retrieval error pathDave Jiang1-11/+12
2023-04-18cxl/pci: Use CDAT DOE mailbox created by PCI coreLukas Wunner1-22/+5
2023-04-18cxl/pci: Use synchronous API for DOELukas Wunner1-44/+22
2023-04-04cxl/pci: Handle excessive CDAT lengthLukas Wunner1-0/+3
2023-04-04cxl/pci: Handle truncated CDAT entriesLukas Wunner1-4/+9
2023-04-04cxl/pci: Handle truncated CDAT headerLukas Wunner1-1/+1
2023-03-21cxl/pci: Fix CDAT retrieval on big endianLukas Wunner1-13/+13
2023-02-17Merge branch 'for-6.3/cxl-events' into cxl/nextDan Williams1-6/+2
2023-02-17cxl/trace: Standardize device information outputIra Weiny1-6/+2
2023-02-15Merge branch 'for-6.3/cxl-rr-emu' into cxl/nextDan Williams1-107/+93
2023-02-15cxl/pci: Remove locked check for dvsec_range_allowed()Dave Jiang1-2/+0
2023-02-15cxl/hdm: Create emulated cxl_hdm for devices that do not have HDM decodersDave Jiang1-3/+6
2023-02-15cxl/hdm: Emulate HDM decoder from DVSEC range registersDave Jiang1-1/+1
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