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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2025-07-17clk: qcom: rpmh: convert from round_rate() to determine_rate()Brian Masney1-4/+4
2025-07-17clk: qcom: rpm: convert from round_rate() to determine_rate()Brian Masney1-5/+5
2025-07-17clk: qcom: gcc-ipq4019: convert from round_rate() to determine_rate()Brian Masney1-6/+8
2025-07-17clk: qcom: videocc-qcs615: Add QCS615 video clock controller driverTaniya Das3-0/+347
2025-07-17clk: qcom: gpucc-qcs615: Add QCS615 graphics clock controller driverTaniya Das3-0/+540
2025-07-17clk: qcom: dispcc-qcs615: Add QCS615 display clock controller driverTaniya Das3-0/+802
2025-07-17clk: qcom: camcc-qcs615: Add QCS615 camera clock controller driverTaniya Das3-0/+1608
2025-07-17clk: qcom: clk-alpha-pll: Add support for dynamic update for slewing PLLsTaniya Das2-18/+175
2025-07-17clk: qcom: gcc-ipq5018: fix GE PHY resetGeorge Moussalem1-1/+1
2025-07-17clk: qcom: gcc-qcm2290: Set HW_CTRL_TRIGGER for video GDSCLoic Poulain1-0/+1
2025-07-17clk: qcom: ipq-cmn-pll: Add IPQ5018 SoC supportGeorge Moussalem1-14/+23
2025-07-17clk: qcom: ipq5018: keep XO clock always onGeorge Moussalem1-1/+1
2025-07-14clk: sunxi-ng: ccu_nm: convert from round_rate() to determine_rate()Brian Masney1-21/+22
2025-07-14clk: sunxi-ng: ccu_nkmp: convert from round_rate() to determine_rate()Brian Masney1-11/+12
2025-07-14clk: sunxi-ng: ccu_nk: convert from round_rate() to determine_rate()Brian Masney1-7/+7
2025-07-14clk: sunxi-ng: ccu_gate: convert from round_rate() to determine_rate()Brian Masney1-6/+8
2025-07-14clk: sunxi-ng: v3s: Assign the de and tcon clocks to the video pllPaul Kocialkowski1-2/+19
2025-07-14clk: sunxi-ng: v3s: Fix de clock definitionPaul Kocialkowski1-2/+1
2025-07-13clk: thead: th1520-ap: Correctly refer the parent of osc_12mYao Zi1-1/+8
2025-07-10clk: rockchip: rk3568: Add PLL rate for 132MHzAndy Yan1-0/+1
2025-07-08clk: renesas: r9a08g045: Add MSTOP for coupled clocks as wellClaudiu Beznea1-2/+4
2025-07-08clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPsJohn Madieu1-0/+64
2025-07-07PM: domains: Add flags to specify power on attach/detachClaudiu Beznea1-1/+1
2025-07-07Merge tag 'spacemit-reset-for-6.17-1' of https://github.com/spacemit-com/linuxYixun Lan2-120/+120
2025-07-04clk: spacemit: mark K1 pll1_d8 as criticalAlex Elder2-4/+10
2025-07-03clk: sunxi-ng: v3s: Fix TCON clock parentsPaul Kocialkowski1-1/+1
2025-07-03clk: sunxi-ng: v3s: Fix CSI1 MCLK clock namePaul Kocialkowski1-1/+1
2025-07-03clk: sunxi-ng: v3s: Fix CSI SCLK clock namePaul Kocialkowski1-5/+5
2025-07-03clk: spacemit: define three reset-only CCUsAlex Elder1-0/+24
2025-07-03clk: spacemit: set up reset auxiliary devicesAlex Elder2-10/+95
2025-07-03soc: spacemit: create a header for clock/reset registersAlex Elder1-110/+1
2025-07-02clk: renesas: r9a09g057: Add XSPI clock/resetLad Prabhakar1-3/+13
2025-07-02clk: renesas: r9a09g056: Add XSPI clock/resetLad Prabhakar2-0/+14
2025-07-02clk: renesas: rzv2h: Add fixed-factor module clocks with status reportingLad Prabhakar2-0/+114
2025-07-02clk: renesas: r9a09g057: Add support for xspi mux and dividerLad Prabhakar1-1/+22
2025-07-02clk: renesas: r9a09g056: Add support for xspi mux and dividerLad Prabhakar1-1/+24
2025-07-02clk: renesas: r9a09g077: Add RIIC module clocksLad Prabhakar1-0/+3
2025-07-02clk: renesas: r9a09g077: Add PLL2 and SDHI clock supportLad Prabhakar1-1/+11
2025-07-02clk: renesas: rzv2h: Drop redundant base pointer from pll_clkLad Prabhakar1-3/+0
2025-07-02clk: renesas: r9a09g057: Add entries for the RSPIsFabrizio Castro1-0/+24
2025-07-02clk: amlogic: s4: remove unused dataJerome Brunet1-112/+0
2025-07-02clk: amlogic: drop clk_regmap tablesJerome Brunet19-2191/+5
2025-07-02clk: amlogic: get regmap with clk_regmap_initJerome Brunet11-0/+89
2025-07-01clk: clk-axi-clkgen: fix coding style issuesNuno Sá1-40/+41
2025-07-01clk: clk-axi-clkgen move to min/max()Nuno Sá1-4/+4
2025-07-01clk: clk-axi-clkgen: detect axi_clkgen_limits at runtimeNuno Sá1-1/+64
2025-07-01clk: clk-axi-clkgen: make sure to include mod_devicetable.hNuno Sá1-0/+1
2025-07-01clk: clk-axi-clkgen: fix fpfd_max frequency for zynqNuno Sá1-1/+1
2025-06-30clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSEDMichal Wilczynski1-2/+3
2025-06-30clk: amlogic: remove unnecessary headersJerome Brunet18-677/+530