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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
9 daysclk: samsung: exynos-clkout: Assign .num before accessing .hwsNathan Chancellor1-1/+1
9 daysclk: mvebu: cp110 add CLK_IGNORE_UNUSED to pcie_x10, pcie_x11 & pcie_x4Josua Mayer1-0/+20
9 daysclk: keystone: fix compile testingJohan Hovold1-2/+1
9 daysclk: renesas: r9a06g032: Fix memory leak in error pathHaotian Zhang1-3/+3
9 daysclk: qcom: camcc-sm6350: Fix PLL config of PLL2Luca Weiss1-5/+1
9 daysclk: qcom: camcc-sm6350: Specify Titan GDSC power domain as a parent to otherVladimir Zapolskiy1-0/+7
9 daysclk: renesas: cpg-mssr: Read back reset registers to assure values latchedMarek Vasut1-25/+21
9 daysclk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_registerThierry Bultel10-71/+88
9 daysclk: renesas: Use str_on_off() helperGeert Uytterhoeven2-2/+4
9 daysclk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()Claudiu Beznea1-1/+1
9 daysclk: renesas: rzg2l: Remove critical areaClaudiu Beznea1-4/+1
9 daysclk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()Claudiu Beznea1-3/+2
9 daysclk: renesas: cpg-mssr: Add missing 1ms delay into reset toggle callbackMarek Vasut1-2/+9
2025-11-24clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabledMatthias Schiffer1-0/+2
2025-11-24clk: at91: clk-sam9x60-pll: force write to PLL_UPDT registerNicolas Ferre1-36/+39
2025-11-24clk: at91: clk-master: Add check for divide by 3Ryan Wanner1-0/+3
2025-11-24clk: sunxi-ng: sun6i-rtc: Add A523 specificsChen-Yu Tsai1-0/+11
2025-10-19clk: tegra: do not overallocate memory for bpmp clocksFedor Pchelkin1-1/+1
2025-10-19clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driverAlok Tiwari1-2/+2
2025-10-19clk: nxp: lpc18xx-cgu: convert from round_rate() to determine_rate()Brian Masney1-7/+9
2025-10-19clk: mediatek: clk-mux: Do not pass flags to clk_mux_determine_rate_flags()Chen-Yu Tsai1-3/+1
2025-10-19clk: mediatek: mt8195-infra_ao: Fix parent for infra_ao_hdmi_26mAngeloGioacchino Del Regno1-1/+1
2025-10-19clk: at91: peripheral: fix return valueBrian Masney1-2/+5
2025-08-28clk: qcom: ipq5018: keep XO clock always onGeorge Moussalem1-1/+1
2025-08-28clk: tegra: periph: Fix error handling and resolve unsigned compare warningPei Xiao1-2/+2
2025-08-15clk: sunxi-ng: v3s: Fix de clock definitionPaul Kocialkowski1-2/+1
2025-08-15clk: clk-axi-clkgen: fix fpfd_max frequency for zynqNuno Sá1-1/+1
2025-08-15clk: xilinx: vcu: unregister pll_post only if registered correctlyRohit Visavalia1-2/+2
2025-08-15clk: davinci: Add NULL check in davinci_lpsc_clk_register()Henry Martin1-0/+5
2025-06-27clk: rockchip: rk3036: mark ddrphy as criticalHeiko Stuebner1-0/+1
2025-06-27clk: meson-g12a: add missing fclk_div2 to spiccDa Xue1-0/+1
2025-06-19clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHzVincent Knecht1-2/+2
2025-06-19clk: bcm: rpi: Add NULL check in raspberrypi_clk_register()Henry Martin1-0/+2
2025-06-19clk: qcom: gpucc-sm6350: Add *_wait_val values for GDSCsLuca Weiss1-0/+6
2025-06-19clk: qcom: gcc-sm6350: Add *_wait_val values for GDSCsLuca Weiss1-0/+6
2025-06-19clk: qcom: dispcc-sm6350: Add *_wait_val values for GDSCsLuca Weiss1-0/+3
2025-06-19clk: qcom: camcc-sm6350: Add *_wait_val values for GDSCsLuca Weiss1-0/+18
2025-06-04clk: s2mps11: initialise clk_hw_onecell_data::num before accessing ::hws[] in...André Draszik1-1/+2
2025-06-04clk: sunxi-ng: d1: Add missing divider for MMC mod clocksAndre Przywara2-19/+47
2025-06-04clk: qcom: camcc-sm8250: Use clk_rcg2_shared_ops for some RCGsJordan Crouse1-28/+28
2025-06-04clk: qcom: clk-alpha-pll: Do not use random stack value for recalc rateKrzysztof Kozlowski1-16/+36
2025-06-04clk: qcom: ipq5018: allow it to be bulid on arm32Karl Chan1-1/+1
2025-06-04clk: imx8mp: inform CCF of maximum frequency of clocksAhmad Fatoum1-0/+151
2025-05-02clk: check for disabled clock-provider in of_clk_get_hw_from_clkspec()Heiko Stuebner1-0/+4
2025-05-02clk: renesas: r9a07g043: Fix HP clock source for RZ/FiveLad Prabhakar1-0/+7
2025-05-02clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variableClaudiu Beznea2-6/+6
2025-05-02clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 muxClaudiu Beznea2-2/+2
2025-05-02clk: renesas: rzg2l: Refactor SD mux driverClaudiu Beznea4-51/+139
2025-05-02clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic headerClaudiu Beznea3-4/+14
2025-05-02clk: renesas: rzg2l: Add struct clk_hw_dataClaudiu Beznea1-18/+34