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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
7 daysclk: keystone: fix compile testingJohan Hovold1-2/+1
7 daysclk: renesas: r9a06g032: Fix memory leak in error pathHaotian Zhang1-3/+3
7 daysclk: qcom: camcc-sm7150: Fix PLL config of PLL2Luca Weiss1-5/+1
7 daysclk: qcom: camcc-sm6350: Fix PLL config of PLL2Luca Weiss1-5/+1
7 daysclk: qcom: camcc-sm6350: Specify Titan GDSC power domain as a parent to otherVladimir Zapolskiy1-0/+7
7 daysclk: qcom: camcc-sm8550: Specify Titan GDSC power domain as a parent to otherVladimir Zapolskiy1-0/+10
7 daysclk: qcom: gcc-x1e80100: Add missing USB4 clocks/resetsKonrad Dybcio1-17/+681
7 daysclk: renesas: cpg-mssr: Read back reset registers to assure values latchedMarek Vasut1-25/+21
7 daysclk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_registerThierry Bultel10-71/+88
7 daysclk: renesas: Use str_on_off() helperGeert Uytterhoeven2-2/+4
7 daysclk: renesas: cpg-mssr: Add missing 1ms delay into reset toggle callbackMarek Vasut1-2/+9
2025-11-13clk: clocking-wizard: Fix output clock register offset for Versal platformsShubhrajyoti Datta1-1/+1
2025-11-13clk: scmi: Add duty cycle ops only when duty cycle is supportedJacky Bai1-2/+9
2025-11-13clk: ti: am33xx: keep WKUP_DEBUGSS_CLKCTRL enabledMatthias Schiffer1-0/+2
2025-11-13clk: at91: clk-sam9x60-pll: force write to PLL_UPDT registerNicolas Ferre1-36/+39
2025-11-13clk: at91: clk-master: Add check for divide by 3Ryan Wanner1-0/+3
2025-11-13clk: at91: sam9x7: Add peripheral clock id for pmeccBalamanikandan Gunasundar1-0/+1
2025-11-13clk: sunxi-ng: sun6i-rtc: Add A523 specificsChen-Yu Tsai1-0/+11
2025-11-13clk: qcom: gcc-ipq6018: rework nss_port5 clock to multiple confMarko Mäkelä1-22/+38
2025-10-19clk: qcom: tcsrcc-x1e80100: Set the bi_tcxo as parent to eDP refclkAbel Vesa1-0/+4
2025-10-19clk: tegra: do not overallocate memory for bpmp clocksFedor Pchelkin1-1/+1
2025-10-19clk: nxp: Fix pll0 rate check condition in LPC18xx CGU driverAlok Tiwari1-2/+2
2025-10-19clk: nxp: lpc18xx-cgu: convert from round_rate() to determine_rate()Brian Masney1-7/+9
2025-10-19clk: mediatek: clk-mux: Do not pass flags to clk_mux_determine_rate_flags()Chen-Yu Tsai1-3/+1
2025-10-19clk: mediatek: mt8195-infra_ao: Fix parent for infra_ao_hdmi_26mAngeloGioacchino Del Regno1-1/+1
2025-10-19clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()Yuan CHen1-2/+5
2025-10-19clk: at91: peripheral: fix return valueBrian Masney1-2/+5
2025-10-19clk: qcom: common: Fix NULL vs IS_ERR() check in qcom_cc_icc_register()Dan Carpenter1-2/+2
2025-08-20clk: qcom: gcc-ipq8074: fix broken freq table for nss_port6_tx_clk_srcChristian Marangi1-3/+3
2025-08-20clk: renesas: rzg2l: Postpone updating priv->clks[]Claudiu Beznea1-4/+4
2025-08-20clk: thead: Mark essential bus clocks as CLK_IGNORE_UNUSEDMichal Wilczynski1-2/+3
2025-08-20clk: qcom: ipq5018: keep XO clock always onGeorge Moussalem1-1/+1
2025-08-20clk: tegra: periph: Fix error handling and resolve unsigned compare warningPei Xiao1-2/+2
2025-08-20clk: samsung: gs101: fix alternate mout_hsi0_usb20_ref parent clockAndré Draszik1-1/+1
2025-08-20clk: samsung: gs101: fix CLK_DOUT_CMU_G3D_BUSDAndré Draszik1-1/+1
2025-08-20clk: samsung: exynos850: fix a commentAndré Draszik1-1/+1
2025-08-15clk: imx95-blk-ctl: Fix synchronous abortLaurentiu Palcu1-6/+7
2025-08-15clk: at91: sam9x7: update pll clk rangesVarshini Rajendran1-10/+10
2025-08-15clk: sunxi-ng: v3s: Fix de clock definitionPaul Kocialkowski1-2/+1
2025-08-15clk: thead: th1520-ap: Correctly refer the parent of osc_12mYao Zi1-1/+8
2025-08-15clk: clk-axi-clkgen: fix fpfd_max frequency for zynqNuno Sá1-1/+1
2025-08-15clk: xilinx: vcu: unregister pll_post only if registered correctlyRohit Visavalia1-2/+2
2025-08-15clk: davinci: Add NULL check in davinci_lpsc_clk_register()Henry Martin1-0/+5
2025-08-15clk: renesas: rzv2h: Fix missing CLK_SET_RATE_PARENT flag for ddiv clocksLad Prabhakar1-0/+1
2025-07-17clk: scmi: Handle case where child clocks are initialized before their parentsSascha Hauer1-8/+10
2025-07-17clk: imx: Fix an out-of-bounds access in dispmix_csr_clk_dev_dataXiaolei Wang1-4/+8
2025-06-27clk: rockchip: rk3036: mark ddrphy as criticalHeiko Stuebner1-0/+1
2025-06-27clk: qcom: gcc-x1e80100: Set FORCE MEM CORE for UFS clocksTaniya Das1-0/+4
2025-06-27clk: meson-g12a: add missing fclk_div2 to spiccDa Xue1-0/+1
2025-06-19clk: qcom: gcc-msm8939: Fix mclk0 & mclk1 for 24 MHzVincent Knecht1-2/+2