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path: root/drivers/clk
AgeCommit message (Expand)AuthorFilesLines
2021-07-19clk: tegra: Ensure that PLLU configuration is applied properlyDmitry Osipenko1-5/+4
2021-07-19clk: tegra: Fix refcounting of gate clocksDmitry Osipenko2-25/+58
2021-07-19clk: renesas: r8a77995: Add ZA2 clockKuninori Morimoto1-0/+1
2021-07-19clk: renesas: rcar-usb2-clock-sel: Fix error handling in .probe()Dinghao Liu1-9/+15
2021-07-14clk: si5341: Update initialization magicRobert Hancock1-1/+3
2021-07-14clk: si5341: Check for input clock presence and PLL lock on startupRobert Hancock1-0/+26
2021-07-14clk: si5341: Avoid divide errors due to bogus register contentsRobert Hancock1-2/+13
2021-07-14clk: si5341: Wait for DEVICE_READY on startupRobert Hancock1-0/+32
2021-07-14clk: qcom: clk-alpha-pll: fix CAL_L write in alpha_pll_fabia_prepareJonathan Marek1-1/+1
2021-07-14clk: actions: Fix AHPPREDIV-H-AHB clock chain on Owl S500 SoCCristian Ciocaltea1-8/+11
2021-07-14clk: actions: Fix bisp_factor_table based clocks on Owl S500 SoCCristian Ciocaltea1-15/+29
2021-07-14clk: actions: Fix SD clocks factor table on Owl S500 SoCCristian Ciocaltea1-4/+2
2021-07-14clk: actions: Fix UART clock dividers on Owl S500 SoCCristian Ciocaltea1-6/+6
2021-07-14clk: imx8mq: remove SYS PLL 1/2 clock gatesLucas Stach1-38/+18
2021-07-14clk: vc5: fix output disabling when enabling a FODLuca Ceresoli1-3/+24
2021-07-14clk: tegra30: Use 300MHz for video decoder by defaultDmitry Osipenko1-1/+1
2021-07-14clk: meson: g12a: fix gp0 and hifi rangesJerome Brunet1-1/+1
2021-07-14clk: agilex/stratix10: fix bypass representationDinh Nguyen2-21/+91
2021-07-14clk: agilex/stratix10: remove noc_clkDinh Nguyen2-34/+30
2021-07-14clk: agilex/stratix10/n5x: fix how the bypass_reg is handledDinh Nguyen1-3/+8
2021-05-19clk: exynos7: Mark aclk_fsys1_200 as criticalPaweł Chmiel1-1/+6
2021-05-14clk: uniphier: Fix potential infinite loopColin Ian King1-2/+2
2021-05-14clk: qcom: apss-ipq-pll: Add missing MODULE_DEVICE_TABLEChen Hui1-0/+1
2021-05-14clk: qcom: a53-pll: Add missing MODULE_DEVICE_TABLEChen Hui1-0/+1
2021-05-14clk: zynqmp: pll: add set_pll_mode to check condition in zynqmp_pll_enableQuanyang Wang1-1/+11
2021-05-14clk: zynqmp: move zynqmp_pll_set_mode out of round_rate callbackQuanyang Wang1-6/+6
2021-05-14clk: imx: Fix reparenting of UARTs not associated with stdoutAdam Ford16-252/+54
2021-05-14media: aspeed: fix clock handling logicJae Hyun Yoo1-2/+2
2021-05-14clk: mvebu: armada-37xx-periph: Fix workaround for switching from L1 to L0Pali Rohár1-6/+39
2021-05-14clk: mvebu: armada-37xx-periph: Fix switching CPU freq from 250 Mhz to 1 GHzPali Rohár1-5/+7
2021-05-14clk: mvebu: armada-37xx-periph: remove .set_parent method for CPU PM clockMarek Behún1-28/+0
2021-05-11clk: socfpga: arria10: Fix memory leak of socfpga_clk on error returnColin Ian King1-0/+1
2021-04-14clk: socfpga: fix iomem pointer cast on 64-bitKrzysztof Kozlowski1-1/+1
2021-04-14clk: fix invalid usage of list cursor in unregisterLukasz Bartosik1-17/+13
2021-04-14clk: fix invalid usage of list cursor in registerLukasz Bartosik1-9/+8
2021-03-30clk: qcom: gcc-sc7180: Use floor ops for the correct sdcc1 clkDouglas Anderson1-2/+2
2021-03-17clk: qcom: gpucc-msm8998: Add resets, cxc, fix flags on gpu_gx_gdscAngeloGioacchino Del Regno1-2/+6
2021-03-17clk: qcom: gdsc: Implement NO_RET_PERIPH flagAngeloGioacchino Del Regno2-3/+10
2021-03-04clk: aspeed: Fix APLL calculate formula from ast2600-A2Ryan Chen1-10/+27
2021-03-04clk: divider: fix initialization with parent_hwMichael Tretter1-2/+7
2021-03-04clk: qcom: gcc-msm8998: Fix Alpha PLL type for all GPLLsAngeloGioacchino Del Regno1-50/+50
2021-03-04clk: sunxi-ng: h6: Fix clock divider range on some clocksAndre Przywara1-4/+4
2021-03-04clk: renesas: r8a779a0: Fix parent of CBFUSA clockGeert Uytterhoeven1-1/+1
2021-03-04clk: renesas: r8a779a0: Remove non-existent S2 clockGeert Uytterhoeven1-1/+0
2021-03-04clk: sunxi-ng: h6: Fix CEC clockAndre Przywara1-1/+1
2021-03-04clk: meson: clk-pll: propagate the error from meson_clk_pll_set_rate()Martin Blumenstingl1-2/+3
2021-03-04clk: meson: clk-pll: make "ret" a signed integerMartin Blumenstingl1-1/+2
2021-03-04clk: meson: clk-pll: fix initializing the old rate (fallback) for a PLLMartin Blumenstingl1-1/+1
2021-02-17clk: sunxi-ng: mp: fix parent rate change flag checkJernej Skrabec1-1/+1
2021-02-04clk: qcom: gcc-sm250: Use floor ops for sdcc clksDmitry Baryshkov1-2/+2