kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2020-05-12	clk: tegra20: Use custom CCLK implementation	Dmitry Osipenko	1	-2/+5
2020-03-12	clk: tegra: Remove audio clocks configuration from clock driver	Sowjanya Komatineni	1	-3/+2
2020-03-12	clk: tegra: Remove tegra_pmc_clk_init along with clk ids	Sowjanya Komatineni	1	-4/+0
2020-01-10	clk: tegra20/30: Explicitly set parent clock for Video Decoder	Dmitry Osipenko	1	-1/+1
2020-01-10	clk: tegra20/30: Don't pre-initialize displays parent clock	Dmitry Osipenko	1	-2/+0
2019-11-11	clk: tegra: Optimize PLLX restore on Tegra20/30	Dmitry Osipenko	1	-9/+16
2019-11-11	clk: tegra: Add Tegra20/30 EMC clock implementation	Dmitry Osipenko	1	-41/+14
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 201	Thomas Gleixner	1	-12/+1
2018-11-08	clk: tegra20: Check whether direct PLLM sourcing is turned off for EMC	Dmitry Osipenko	1	-0/+10
2018-11-08	clk: tegra20: Turn EMC clock gate into divider	Dmitry Osipenko	1	-10/+26
2018-05-18	clk: tegra: Add quirk for getting CDEV1/2 clocks on Tegra20	Dmitry Osipenko	1	-1/+31
2018-05-18	clk: tegra20: Correct parents of CDEV1/2 clocks	Dmitry Osipenko	1	-4/+2
2018-05-18	clk: tegra20: Add DEV1/DEV2 OSC dividers	Dmitry Osipenko	1	-0/+14
2018-03-12	clk: tegra: Specify VDE clock rate	Dmitry Osipenko	1	-0/+1
2018-03-12	clk: tegra20: Correct PLL_C_OUT1 setup	Dmitry Osipenko	1	-3/+3
2018-03-12	clk: tegra: Mark HCLK, SCLK and EMC as critical	Dmitry Osipenko	1	-13/+10
2017-11-01	clk: tegra: Bump SCLK clock rate to 216 MHz	Dmitry Osipenko	1	-1/+1
2017-11-01	clk: tegra: Use common definition of APBDMA clock gate	Dmitry Osipenko	1	-5/+1
2017-11-01	clk: tegra: Add AHB DMA clock entry	Dmitry Osipenko	1	-0/+1
2017-10-19	clk: tegra: Use tegra_clk_register_periph_data()	Thierry Reding	1	-3/+1
2016-04-28	treewide: Fix typos in printk	Masanari Iida	1	-1/+1
2016-03-03	clk: tegra: Remove CLK_IS_ROOT	Stephen Boyd	1	-6/+4
2015-11-20	clk: tegra: pll: Fix _pll_ramp_calc_pll logic and _calc_dynamic_ramp_rate	Rhyland Klein	1	-72/+78
2015-11-20	clk: tegra: pll: Don't unconditionally set LOCK flags	Rhyland Klein	1	-8/+10
2015-11-20	clk: tegra: Constify pdiv-to-hw mappings	Thierry Reding	1	-1/+1
2015-11-18	clk: tegra: Format tables consistently	Thierry Reding	1	-143/+134
2015-11-18	clk: tegra: Miscellaneous coding style cleanups	Thierry Reding	1	-3/+2
2015-07-20	clk: tegra: Properly include clk.h	Stephen Boyd	1	-1/+0
2014-11-26	clk: tegra: Implement memory-controller clock	Thierry Reding	1	-1/+7
2014-02-17	clk: tegra: Add missing Tegra20 fuse clks	Peter De Schrijver	1	-0/+2
2013-12-12	clk: tegra: remove bogus PCIE_XCLK	Stephen Warren	1	-6/+0
2013-12-12	clk: tegra: implement a reset driver	Stephen Warren	1	-1/+2
2013-11-26	clk: tegra: add FUSE clock device	Alexandre Courbot	1	-0/+1
2013-11-26	clk: tegra: move tegra20 to common infra	Peter De Schrijver	1	-402/+255
2013-11-26	clk: tegra: move periph clocks to common file	Peter De Schrijver	1	-2/+2
2013-11-26	clk: tegra: move fields to tegra_clk_pll_params	Peter De Schrijver	1	-17/+27
2013-11-26	clk: tegra: common periph_clk_enb_refcnt and clks	Peter De Schrijver	1	-27/+9
2013-11-26	clk: tegra: simplify periph clock data	Peter De Schrijver	1	-138/+82
2013-08-19	clk: add CLK_SET_RATE_NO_REPARENT flag	James Hogan	1	-2/+4
2013-08-09	clk: tegra20: Fix incorrect placement of __initdata	Sachin Kamat	1	-1/+1
2013-05-31	clk: tegra: Use common of_clk_init function	Prashant Gaikwad	1	-1/+2
2013-05-21	clk: tegra: add ac97 controller clock	Lucas Stach	1	-0/+8
2013-05-21	clk: tegra: remove USB from clk init table	Lucas Stach	1	-3/+0
2013-05-04	Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/gi...	Linus Torvalds	1	-85/+99
2013-05-02	Merge tag 'fixes-nc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/g...	Linus Torvalds	1	-34/+2
2013-04-09	Merge tag 'tegra-for-3.10-fixes' of git://git.kernel.org/pub/scm/linux/kernel...	Arnd Bergmann	1	-34/+2
2013-04-05	clk: tegra: Add flags to tegra_clk_periph()	Peter De Schrijver	1	-1/+1
2013-04-05	clk: tegra: move from a lock bit idx to a lock mask	Peter De Schrijver	1	-10/+10
2013-04-05	clk: tegra: Add PLL post divider table	Peter De Schrijver	1	-0/+7
2013-04-05	clk: tegra: Refactor PLL programming code	Peter De Schrijver	1	-72/+72