Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2015-07-18 | Update Viresh Kumar's email address | Viresh Kumar | 1 | -1/+1 |
2012-11-21 | CLK: SPEAr: Correct index scanning done for clock synths | Deepak Sikri | 1 | -0/+3 |
2012-06-21 | Viresh has moved | Viresh Kumar | 1 | -1/+1 |
2012-05-12 | SPEAr: clk: Add VCO-PLL Synthesizer clock | Viresh Kumar | 1 | -0/+36 |