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path: root/drivers/clk/rockchip
AgeCommit message (Expand)AuthorFilesLines
2024-10-10clk: rockchip: fix finding of maximum clock IDYao Zi1-1/+1
2024-09-10clk: rockchip: remove unused mclk_pdm0_p/pdm0_p definitionsArnd Bergmann1-2/+0
2024-08-30clk: rockchip: fix error for unknown clocksSebastian Reichel1-1/+2
2024-08-30clk: rockchip: rk3588: drop unused codeSebastian Reichel1-40/+0
2024-08-29clk: rockchip: Add clock controller for the RK3576Elaine Zhang5-0/+2532
2024-08-29clk: rockchip: Add new pll type pll_rk3588_ddrElaine Zhang2-1/+6
2024-08-29clk: rockchip: rk3588: Fix 32k clock name for pmu_24m_32k_100m_src_pAlexander Shiyan1-1/+1
2024-08-28clk: rockchip: rk3399: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usageJohan Jonker1-2/+8
2024-08-28clk: rockchip: rk3368: Drop CLK_NR_CLKS usageJohan Jonker1-1/+4
2024-08-28clk: rockchip: rk3328: Drop CLK_NR_CLKS usageJohan Jonker1-1/+4
2024-08-28clk: rockchip: rk3308: Drop CLK_NR_CLKS usageJohan Jonker1-1/+4
2024-08-28clk: rockchip: rk3288: Drop CLK_NR_CLKS usageJohan Jonker1-1/+4
2024-08-28clk: rockchip: rk3228: Drop CLK_NR_CLKS usageJohan Jonker1-1/+4
2024-08-28clk: rockchip: rk3036: Drop CLK_NR_CLKS usageJohan Jonker1-1/+4
2024-08-28clk: rockchip: px30: Drop CLK_NR_CLKS CLKPMU_NR_CLKS usageJohan Jonker1-2/+8
2024-07-29clk: rockchip: Set parent rate for DCLK_VOP clock on RK3228Jonas Karlman1-1/+1
2024-06-27clk: rockchip: rk3188: Drop CLK_NR_CLKS usageJohan Jonker1-4/+14
2024-06-23clk: rockchip: Switch to use kmemdup_array()Andy Shevchenko2-7/+6
2024-06-23clk: rockchip: rk3128: Add HCLK_SFCAlex Bee1-0/+1
2024-06-08clk: rockchip: rk3128: Drop CLK_NR_CLKS usageAlex Bee1-4/+16
2024-05-28clk: rockchip: rk3128: Add hclk_vio_h2p to critical clocksAlex Bee1-0/+1
2024-05-28clk: rockchip: rk3128: Export PCLK_MIPIPHYAlex Bee1-1/+1
2024-05-04clk: rockchip: rk3568: Add PLL rate for 724 MHzLucas Stach1-0/+1
2024-05-04clk: rockchip: Remove an unused field in struct rockchip_mmc_clockChristophe JAILLET1-1/+0
2024-04-10clk: rockchip: rk3588: Add reset line for HDMI ReceiverShreeya Patel1-0/+1
2024-04-10clk: rockchip: rk3568: Add missing USB480M_PHY muxDavid Jander1-0/+4
2024-02-28clk: rockchip: rk3399: Allow to set rate of clk_i2s0_frac's parentOndrej Jirman1-3/+3
2024-02-28clk: rockchip: rk3588: use linked clock ID for GATE_LINKSebastian Reichel1-23/+23
2024-02-28clk: rockchip: rk3588: fix indentSebastian Reichel1-1/+1
2024-02-28clk: rockchip: rk3588: fix pclk_vo0grf and pclk_vo1grfSebastian Reichel1-6/+4
2024-02-28Merge branch 'v6.9-shared/clkids' into v6.9-clk/nextHeiko Stuebner3-1/+23
2024-02-27clk: rockchip: rk3588: fix CLK_NR_CLKS usageSebastian Reichel3-1/+23
2024-01-25clk: rockchip: rk3568: Add PLL rate for 128MHzChris Morgan1-0/+1
2024-01-13Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...Linus Torvalds1-0/+3
2023-12-05clk: rockchip: rk3568: Mark pclk_usb as criticalChris Morgan1-0/+1
2023-12-05clk: rockchip: rk3568: Add PLL rate for 126.4MHzChris Morgan1-0/+1
2023-11-28clk: rockchip: rk3128: Fix SCLK_SDMMC's clock nameAlex Bee1-1/+1
2023-11-28clk: rockchip: rk3128: Fix aclk_peri_src's parentFinley Xiao1-13/+7
2023-11-16clk: rockchip: rk3128: Fix HCLK_OTG gate registerWeihao Li1-1/+1
2023-11-16clk: rockchip: rk3568: Add PLL rate for 292.5MHzChris Morgan1-0/+1
2023-11-16clk: rockchip: rk3568: Add PLL rate for 115.2MHzChris Morgan1-0/+1
2023-10-24clk: Use device_get_match_data()Rob Herring1-7/+2
2023-08-31Merge branches 'clk-versa', 'clk-strdup', 'clk-amlogic', 'clk-allwinner' and ...Stephen Boyd2-1/+61
2023-08-11clk: rockchip: rv1126: Add PD_VO clock treeJagan Teki1-0/+59
2023-07-19clk: Explicitly include correct DT includesRob Herring2-2/+2
2023-07-10clk: rockchip: rk3568: Fix PLL rate setting for 78.75MHzAlibek Omarov1-1/+1
2023-07-10clk: rockchip: rk3568: Add PLL rate for 101MHzAlibek Omarov1-0/+1
2023-04-25Merge branches 'clk-of', 'clk-samsung', 'clk-rockchip' and 'clk-qcom' into cl...Stephen Boyd2-17/+27
2023-04-18clk: rockchip: rk3588: make gate linked clocks criticalSebastian Reichel1-16/+26
2023-04-05clk: rockchip: Remove values for mmask and nmask in struct clk_fractional_div...Christophe JAILLET1-2/+0