kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2026-03-04	clk: renesas: rzg2l: Select correct div round macro	Chris Brandt	1	-2/+2
2026-03-04	clk: renesas: rzg2l: Fix intin variable size	Chris Brandt	1	-1/+1
2025-12-18	clk: renesas: r9a06g032: Fix memory leak in error path	Haotian Zhang	1	-3/+3
2025-12-18	clk: renesas: cpg-mssr: Read back reset registers to assure values latched	Marek Vasut	1	-25/+21
2025-12-18	clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register	Thierry Bultel	10	-71/+88
2025-12-18	clk: renesas: Use str_on_off() helper	Geert Uytterhoeven	2	-2/+4
2025-12-18	clk: renesas: cpg-mssr: Add missing 1ms delay into reset toggle callback	Marek Vasut	1	-2/+9
2025-10-19	clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()	Yuan CHen	1	-2/+5
2025-08-20	clk: renesas: rzg2l: Postpone updating priv->clks[]	Claudiu Beznea	1	-4/+4
2025-08-15	clk: renesas: rzv2h: Fix missing CLK_SET_RATE_PARENT flag for ddiv clocks	Lad Prabhakar	1	-0/+1
2025-05-29	clk: renesas: rzg2l-cpg: Refactor Runtime PM clock validation	Lad Prabhakar	1	-48/+54
2025-04-20	clk: renesas: r9a07g043: Fix HP clock source for RZ/Five	Lad Prabhakar	1	-0/+7
2025-04-10	clk: renesas: r8a08g045: Check the source of the CPU PLL settings	Claudiu Beznea	3	-6/+22
2025-02-08	clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init()	Javier Carrasco	1	-1/+1
2024-12-05	clk: renesas: rzg2l: Fix FOUTPOSTDIV clk	Biju Das	1	-5/+6
2024-09-22	clk: Switch back to struct platform_driver::remove()	Uwe Kleine-König	1	-1/+1
2024-09-22	Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-next	Stephen Boyd	14	-187/+1526
2024-09-02	clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT	Lad Prabhakar	2	-0/+88
2024-09-02	clk: renesas: rzv2h: Add support for dynamic switching divider clocks	Lad Prabhakar	2	-3/+201
2024-09-02	clk: renesas: r9a08g045: Add clocks, resets and power domains for USB	Claudiu Beznea	1	-0/+17
2024-08-20	clk: renesas: r8a779h0: Add CANFD clock	Cong Dang	1	-0/+1
2024-08-20	clk: renesas: Add RZ/V2H(P) CPG driver	Lad Prabhakar	5	-0/+94
2024-08-03	clk: Use of_property_present()	Rob Herring (Arm)	1	-1/+1
2024-08-02	clk: renesas: Add family-specific clock driver for RZ/V2H(P)	Lad Prabhakar	4	-0/+838
2024-08-02	clk: renesas: r8a779h0: Add PWM clock	Cong Dang	1	-0/+1
2024-07-30	clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs	Geert Uytterhoeven	5	-28/+20
2024-07-30	clk: renesas: rcar-gen4: Remove unused fixed PLL clock types	Geert Uytterhoeven	2	-24/+0
2024-07-30	clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type	Geert Uytterhoeven	2	-10/+0
2024-07-30	clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs	Geert Uytterhoeven	1	-5/+5
2024-07-30	clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs	Geert Uytterhoeven	1	-7/+7
2024-07-30	clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs	Geert Uytterhoeven	1	-6/+6
2024-07-30	clk: renesas: r8a779a0: Use defines for PLL control registers	Geert Uytterhoeven	1	-4/+9
2024-07-30	clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs	Geert Uytterhoeven	2	-0/+44
2024-07-30	clk: renesas: rcar-gen4: Add support for fixed variable PLLs	Geert Uytterhoeven	2	-10/+26
2024-07-30	clk: renesas: rcar-gen4: Add support for variable fractional PLLs	Geert Uytterhoeven	2	-7/+18
2024-07-30	clk: renesas: rcar-gen4: Add support for fractional multiplication	Geert Uytterhoeven	1	-16/+55
2024-07-30	clk: renesas: rcar-gen4: Use defines for common CPG registers	Geert Uytterhoeven	5	-21/+27
2024-07-30	clk: renesas: rcar-gen4: Use FIELD_GET()	Geert Uytterhoeven	2	-5/+11
2024-07-30	clk: renesas: rcar-gen4: Clarify custom PLL clock support	Geert Uytterhoeven	1	-15/+17
2024-07-30	clk: renesas: rcar-gen4: Removed unused SSMODE_* definitions	Geert Uytterhoeven	1	-4/+0
2024-07-30	clk: renesas: rzg2l-cpg: Refactor to use priv for clks and base in clock regi...	Lad Prabhakar	1	-28/+17
2024-07-30	clk: renesas: rzg2l-cpg: Use devres API to register clocks	Lad Prabhakar	1	-6/+20
2024-07-30	clk: renesas: r8a779h0: Initial clock descriptions should be __initconst	Geert Uytterhoeven	1	-3/+3
2024-07-30	clk: renesas: r8a779g0: cpg_pll_configs should be __initconst	Geert Uytterhoeven	1	-1/+1
2024-07-30	clk: renesas: r8a779f0: cpg_pll_configs should be __initconst	Geert Uytterhoeven	1	-1/+1
2024-07-30	clk: renesas: r8a779a0: cpg_pll_configs should be __initconst	Geert Uytterhoeven	1	-1/+1
2024-07-30	clk: renesas: r9a08g045: Add DMA clocks and resets	Claudiu Beznea	1	-0/+3
2024-07-30	clk: renesas: r9a07g043: Add LCDC clock and reset entries	Biju Das	1	-0/+12
2024-07-30	clk: renesas: r8a779h0: Add PCIe clock	Yoshihiro Shimoda	1	-0/+1
2024-06-27	clk: renesas: r9a08g045: Add clock, reset and power domain support for I2C	Claudiu Beznea	1	-0/+20