kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
9 days	clk: renesas: r9a06g032: Fix memory leak in error path	Haotian Zhang	1	-3/+3
9 days	clk: renesas: cpg-mssr: Read back reset registers to assure values latched	Marek Vasut	1	-25/+21
9 days	clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_register	Thierry Bultel	10	-71/+88
9 days	clk: renesas: Use str_on_off() helper	Geert Uytterhoeven	2	-2/+4
9 days	clk: renesas: rzg2l: Use %x format specifier to print CLK_ON_R()	Claudiu Beznea	1	-1/+1
9 days	clk: renesas: rzg2l: Remove critical area	Claudiu Beznea	1	-4/+1
9 days	clk: renesas: rzg2l: Simplify the logic in rzg2l_mod_clock_endisable()	Claudiu Beznea	1	-3/+2
9 days	clk: renesas: cpg-mssr: Add missing 1ms delay into reset toggle callback	Marek Vasut	1	-2/+9
2025-05-02	clk: renesas: r9a07g043: Fix HP clock source for RZ/Five	Lad Prabhakar	1	-0/+7
2025-05-02	clk: renesas: r9a07g04[34]: Fix typo for sel_shdi variable	Claudiu Beznea	2	-6/+6
2025-05-02	clk: renesas: r9a07g04[34]: Use SEL_SDHI1_STS status configuration for SD1 mux	Claudiu Beznea	2	-2/+2
2025-05-02	clk: renesas: rzg2l: Refactor SD mux driver	Claudiu Beznea	4	-51/+139
2025-05-02	clk: renesas: rzg2l: Remove CPG_SDHI_DSEL from generic header	Claudiu Beznea	3	-4/+14
2025-05-02	clk: renesas: rzg2l: Add struct clk_hw_data	Claudiu Beznea	1	-18/+34
2025-05-02	clk: renesas: rzg2l: Use u32 for flag and mux_flags	Claudiu Beznea	1	-2/+2
2024-12-09	clk: renesas: rzg2l: Fix FOUTPOSTDIV clk	Biju Das	1	-5/+6
2024-06-12	clk: renesas: r9a07g043: Add clock and reset entry for PLIC	Lad Prabhakar	1	-0/+9
2024-06-12	clk: renesas: r8a779a0: Fix CANFD parent clock	Geert Uytterhoeven	1	-1/+1
2024-03-27	clk: renesas: r8a779f0: Correct PFC/GPIO parent clock	Geert Uytterhoeven	1	-1/+1
2024-03-27	clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks	Geert Uytterhoeven	1	-5/+6
2024-01-26	clk: renesas: rzg2l: Check reset monitor registers	Claudiu Beznea	1	-15/+44
2024-01-26	clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()	Claudiu Beznea	1	-23/+15
2023-11-20	clk: renesas: rzg2l: Fix computation formula	Claudiu Beznea	1	-6/+6
2023-11-20	clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields	Claudiu Beznea	1	-5/+5
2023-11-20	clk: renesas: rzg2l: Trust value returned by hardware	Claudiu Beznea	1	-7/+1
2023-11-20	clk: renesas: rzg2l: Lock around writes to mux register	Claudiu Beznea	2	-11/+14
2023-11-20	clk: renesas: rzg2l: Wait for status bit of SD mux before continuing	Claudiu Beznea	1	-7/+10
2023-11-20	clk: renesas: rcar-gen3: Extend SDnH divider table	Dirk Behme	1	-1/+14
2023-08-31	Merge branches 'clk-bindings', 'clk-starfive', 'clk-rm', 'clk-renesas' and 'c...	Stephen Boyd	17	-19/+73
2023-08-15	clk: renesas: rcar-gen3: Add ADG clocks	Kuninori Morimoto	9	-1/+9
2023-07-27	clk: renesas: r8a77965: Add 3DGE and ZG support	Geert Uytterhoeven	1	-0/+2
2023-07-27	clk: renesas: r8a7796: Add 3DGE and ZG support	Geert Uytterhoeven	1	-0/+2
2023-07-27	clk: renesas: r8a7795: Add 3DGE and ZG support	Geert Uytterhoeven	1	-0/+2
2023-07-27	clk: renesas: emev2: Remove obsolete clkdev registration	Geert Uytterhoeven	1	-3/+0
2023-07-25	clk: renesas: r9a07g043: Add MTU3a clock and reset entry	Biju Das	1	-0/+3
2023-07-19	clk: Explicitly include correct DT includes	Rob Herring	3	-4/+1
2023-07-11	clk: renesas: rzg2l: Simplify .determine_rate()	Christophe JAILLET	1	-7/+1
2023-07-10	clk: renesas: r9a09g011: Add CSI related clocks	Fabrizio Castro	1	-0/+15
2023-07-10	clk: renesas: r8a774b1: Add 3DGE and ZG support	Adam Ford	1	-0/+2
2023-07-10	clk: renesas: r8a774e1: Add 3DGE and ZG support	Adam Ford	1	-0/+2
2023-07-10	clk: renesas: r8a774a1: Add 3DGE and ZG support	Adam Ford	1	-0/+2
2023-07-10	clk: renesas: rcar-gen3: Add support for ZG clock	Adam Ford	2	-4/+32
2023-06-26	Merge branches 'clk-renesas', 'clk-determine-rate', 'clk-allwinner', 'clk-sam...	Stephen Boyd	6	-49/+27
2023-06-09	clk: renesas: r9a06g032: Add a determine_rate hook	Maxime Ripard	1	-0/+1
2023-06-05	clk: renesas: rzg2l: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-11/+5
2023-06-05	clk: renesas: mstp: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-11/+7
2023-06-05	clk: renesas: cpg-mssr: Convert to readl_poll_timeout_atomic()	Geert Uytterhoeven	1	-20/+11
2023-05-23	clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write	Biju Das	2	-7/+2
2023-05-08	clk: renesas: r8a779a0: Add PWM clock	Wolfram Sang	1	-0/+1
2023-04-30	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	7	-204/+591