kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2025-12-18	clk: renesas: r9a06g032: Fix memory leak in error path	Haotian Zhang	1	-3/+3
2025-12-18	clk: renesas: r9a09g077: Propagate rate changes to parent clocks	Lad Prabhakar	1	-2/+2
2025-12-18	clk: renesas: cpg-mssr: Read back reset registers to assure values latched	Marek Vasut	1	-25/+21
2025-12-18	clk: renesas: cpg-mssr: Add missing 1ms delay into reset toggle callback	Marek Vasut	1	-2/+9
2025-09-12	clk: renesas: r9a09g05[67]: Reduce differences	Geert Uytterhoeven	2	-6/+5
2025-09-12	clk: renesas: r9a09g047: Add USB3.0 clocks/resets	Biju Das	1	-1/+8
2025-09-12	clk: renesas: cpg-mssr: Fix memory leak in cpg_mssr_reserved_init()	Yuan CHen	1	-2/+5
2025-09-11	clk: renesas: r9a09g056: Add clock and reset entries for I3C	Lad Prabhakar	1	-0/+8
2025-09-11	clk: renesas: r9a09g057: Add clock and reset entries for I3C	Lad Prabhakar	1	-0/+8
2025-09-04	clk: renesas: r9a09g077: Add Ethernet Subsystem core and module clocks	Lad Prabhakar	1	-1/+13
2025-09-04	clk: renesas: rzv2h: Simplify polling condition in __rzv2h_cpg_assert()	Tommaso Merciai	1	-2/+1
2025-09-04	clk: renesas: rzv2h: Re-assert reset on deassert timeout	Tommaso Merciai	1	-3/+10
2025-09-04	clk: renesas: rzg2l: Re-assert reset on deassert timeout	Tommaso Merciai	1	-2/+8
2025-09-04	clk: renesas: rzg2l: Simplify rzg2l_cpg_assert() and rzg2l_cpg_deassert()	Tommaso Merciai	1	-29/+15
2025-08-25	clk: renesas: r9a09g047: Add GPT clocks and resets	Biju Das	1	-0/+8
2025-08-20	clk: renesas: r9a09g077: Add module clocks for SCI1-SCI5	Lad Prabhakar	1	-0/+25
2025-08-20	clk: renesas: rzv2h: remove round_rate() in favor of determine_rate()	Brian Masney	1	-10/+0
2025-08-20	clk: renesas: rzg2l: convert from round_rate() to determine_rate()	Brian Masney	1	-5/+4
2025-08-20	clk: renesas: r9a07g04[34]: Use tabs instead of spaces	Claudiu Beznea	2	-8/+8
2025-08-20	clk: renesas: r9a07g043: Add MSTOP for RZ/G2UL	Claudiu Beznea	1	-66/+66
2025-08-20	clk: renesas: r9a07g044: Add MSTOP for RZ/G2L	Claudiu Beznea	2	-77/+78
2025-08-20	clk: renesas: r9a08g045: Add MSTOP for GPIO	Claudiu Beznea	1	-1/+2
2025-08-20	clk: renesas: r9a09g077: Add USB core and module clocks	Lad Prabhakar	1	-1/+3
2025-08-20	clk: renesas: r9a09g047: Add DMAC clocks and resets	Tommaso Merciai	1	-0/+19
2025-08-20	clk: renesas: r9a08g045: Add PCIe clocks and resets	Claudiu Beznea	1	-0/+19
2025-08-20	clk: renesas: r9a08g045: Add I3C clocks and resets	Wolfram Sang	1	-0/+7
2025-08-18	clk: renesas: mstp: Add genpd OF provider at postcore_initcall()	Geert Uytterhoeven	1	-1/+19
2025-07-08	clk: renesas: r9a08g045: Add MSTOP for coupled clocks as well	Claudiu Beznea	1	-2/+4
2025-07-08	clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPs	John Madieu	1	-0/+64
2025-07-02	clk: renesas: r9a09g057: Add XSPI clock/reset	Lad Prabhakar	1	-3/+13
2025-07-02	clk: renesas: r9a09g056: Add XSPI clock/reset	Lad Prabhakar	2	-0/+14
2025-07-02	clk: renesas: rzv2h: Add fixed-factor module clocks with status reporting	Lad Prabhakar	2	-0/+114
2025-07-02	clk: renesas: r9a09g057: Add support for xspi mux and divider	Lad Prabhakar	1	-1/+22
2025-07-02	clk: renesas: r9a09g056: Add support for xspi mux and divider	Lad Prabhakar	1	-1/+24
2025-07-02	clk: renesas: r9a09g077: Add RIIC module clocks	Lad Prabhakar	1	-0/+3
2025-07-02	clk: renesas: r9a09g077: Add PLL2 and SDHI clock support	Lad Prabhakar	1	-1/+11
2025-07-02	clk: renesas: rzv2h: Drop redundant base pointer from pll_clk	Lad Prabhakar	1	-3/+0
2025-07-02	clk: renesas: r9a09g057: Add entries for the RSPIs	Fabrizio Castro	1	-0/+24
2025-06-26	clk: renesas: rzv2h: Add missing include file	Fabrizio Castro	1	-0/+1
2025-06-24	clk: renesas: rzv2h: Use devm_kmemdup_array()	Raag Jadav	1	-2/+2
2025-06-19	clk: renesas: Add CPG/MSSR support to RZ/N2H SoC	Lad Prabhakar	4	-0/+13
2025-06-19	clk: renesas: r9a09g077: Add PCLKL core clock	Lad Prabhakar	1	-1/+2
2025-06-19	clk: renesas: r9a09g047: Add I3C0 clocks and resets	Tommaso Merciai	1	-0/+8
2025-06-13	clk: renesas: rzv2h: Fix missing CLK_SET_RATE_PARENT flag for ddiv clocks	Lad Prabhakar	1	-0/+1
2025-06-10	clk: renesas: rzg2l: Rename mstp_clock to mod_clock	Geert Uytterhoeven	1	-22/+22
2025-06-10	clk: renesas: r9a09g056: Add clock and reset entries for USB2.0	Lad Prabhakar	1	-0/+10
2025-06-10	clk: renesas: rzg2l: Drop MSTOP based power domain support	Claudiu Beznea	2	-242/+17
2025-06-10	clk: renesas: r9a08g045: Drop power domain instantiation	Claudiu Beznea	1	-123/+93
2025-06-10	clk: renesas: rzg2l: Add support for MSTOP in clock enable/disable API	Claudiu Beznea	6	-266/+517
2025-06-10	clk: renesas: rzg2l: Add macro to loop through module clocks	Claudiu Beznea	1	-9/+9