kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2024-12-14	clk: renesas: rzg2l: Fix FOUTPOSTDIV clk	Biju Das	1	-5/+6
2024-06-12	clk: renesas: r9a07g043: Add clock and reset entry for PLIC	Lad Prabhakar	1	-0/+9
2024-06-12	clk: renesas: r8a779a0: Fix CANFD parent clock	Geert Uytterhoeven	1	-1/+1
2024-03-27	clk: renesas: r8a779f0: Correct PFC/GPIO parent clock	Geert Uytterhoeven	1	-1/+1
2024-03-27	clk: renesas: r8a779g0: Correct PFC/GPIO parent clocks	Geert Uytterhoeven	1	-5/+6
2024-03-27	clk: renesas: r8a779g0: Add thermal clock	Geert Uytterhoeven	1	-0/+1
2024-03-27	clk: renesas: r8a779g0: Add Audio clocks	Kuninori Morimoto	1	-0/+2
2024-03-27	clk: renesas: r8a779g0: Add CMT clocks	Wolfram Sang	1	-0/+4
2024-01-26	clk: renesas: rzg2l: Check reset monitor registers	Claudiu Beznea	1	-15/+44
2024-01-26	clk: renesas: rzg2l-cpg: Reuse code in rzg2l_cpg_reset()	Claudiu Beznea	1	-23/+15
2023-11-20	clk: renesas: rzg2l: Fix computation formula	Claudiu Beznea	1	-6/+6
2023-11-20	clk: renesas: rzg2l: Use FIELD_GET() for PLL register fields	Claudiu Beznea	1	-5/+5
2023-11-20	clk: renesas: rzg2l: Trust value returned by hardware	Claudiu Beznea	1	-7/+1
2023-11-20	clk: renesas: rzg2l: Lock around writes to mux register	Claudiu Beznea	2	-11/+14
2023-11-20	clk: renesas: rzg2l: Wait for status bit of SD mux before continuing	Claudiu Beznea	1	-7/+10
2023-11-20	clk: renesas: rcar-gen3: Extend SDnH divider table	Dirk Behme	1	-1/+14
2023-07-19	clk: renesas: rzg2l: Fix CPG_SIPLL5_CLK1 register write	Biju Das	2	-7/+2
2023-03-17	clk: renesas: rcar-gen3: Disable R-Car H3 ES1.*	Wolfram Sang	5	-173/+13
2022-12-31	clk: renesas: r8a779f0: Fix SCIF parent clocks	Wolfram Sang	1	-4/+4
2022-12-31	clk: renesas: r8a779f0: Fix HSCIF parent clocks	Wolfram Sang	1	-4/+4
2022-12-31	clk: renesas: r9a06g032: Repair grave increment error	Marek Vasut	1	-2/+1
2022-12-31	clk: renesas: r8a779a0: Fix SD0H clock name	Wolfram Sang	1	-1/+1
2022-12-31	clk: renesas: r8a779f0: Fix SD0H clock name	Geert Uytterhoeven	1	-1/+1
2022-10-26	clk: renesas: r8a779g0: Fix HSCIF parent clocks	Geert Uytterhoeven	1	-4/+4
2022-10-18	clk: renesas: r8a779g0: Add SASYNCPER clocks	Geert Uytterhoeven	1	-0/+5
2022-09-18	clk: renesas: r8a779g0: Add EtherAVB clocks	Geert Uytterhoeven	1	-0/+3
2022-09-18	clk: renesas: r8a779g0: Add PFC/GPIO clocks	Geert Uytterhoeven	1	-0/+4
2022-09-18	clk: renesas: r8a779g0: Add I2C clocks	Geert Uytterhoeven	1	-0/+6
2022-09-18	clk: renesas: r8a779g0: Add watchdog clock	Geert Uytterhoeven	1	-0/+1
2022-08-29	clk: renesas: r8a779f0: Add MSIOF clocks	Wolfram Sang	1	-0/+4
2022-08-29	clk: renesas: r9a09g011: Add IIC clock and reset entries	Phil Edworthy	1	-0/+4
2022-08-22	clk: renesas: r9a07g044: Add conditional compilation for r9a07g044_cpg_info	Biju Das	1	-0/+2
2022-08-22	clk: renesas: r8a779f0: Add TMU and parent SASYNC clocks	Wolfram Sang	1	-0/+10
2022-08-15	clk: renesas: r8a779f0: Add CMT clocks	Wolfram Sang	1	-0/+4
2022-08-15	clk: renesas: r8a779f0: Add SDH0 clock	Wolfram Sang	1	-1/+2
2022-07-05	clk: renesas: rcar-gen4: Fix initconst confusion for cpg_pll_config	Andi Kleen	1	-1/+1
2022-07-05	clk: renesas: r9a07g043: Add support for RZ/Five SoC	Lad Prabhakar	1	-0/+32
2022-06-17	clk: renesas: r8a779f0: Add HSCIF clocks	Wolfram Sang	1	-0/+4
2022-06-17	clk: renesas: r8a779f0: Add PCIe clocks	Yoshihiro Shimoda	1	-0/+2
2022-06-17	clk: renesas: r8a779f0: Add Z0 and Z1 clock support	Geert Uytterhoeven	1	-0/+2
2022-06-13	clk: renesas: rza1: Remove struct rz_cpg	Geert Uytterhoeven	1	-18/+15
2022-06-13	clk: renesas: r8a7779: Remove struct r8a7779_cpg	Geert Uytterhoeven	1	-18/+9
2022-06-13	clk: renesas: r8a7778: Remove struct r8a7778_cpg	Geert Uytterhoeven	1	-22/+9
2022-06-13	clk: renesas: sh73a0: Remove sh73a0_cpg.reg	Geert Uytterhoeven	1	-13/+13
2022-06-13	clk: renesas: r8a7740: Remove r8a7740_cpg.reg	Geert Uytterhoeven	1	-10/+10
2022-06-13	clk: renesas: r8a73a4: Remove r8a73a4_cpg.reg	Geert Uytterhoeven	1	-11/+11
2022-06-13	clk: renesas: r8a779f0: Add SDHI0 clock	Wolfram Sang	1	-0/+1
2022-06-13	clk: renesas: r8a779f0: Add thermal clock	Wolfram Sang	1	-0/+1
2022-06-07	clk: renesas: rzg2l: Fix reset status function	Biju Das	1	-1/+1
2022-06-06	clk: renesas: r9a06g032: Fix UART clkgrp bitsel	Ralph Siemsen	1	-4/+4