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path: root/drivers/clk/renesas
AgeCommit message (Expand)AuthorFilesLines
2025-07-08clk: renesas: r9a08g045: Add MSTOP for coupled clocks as wellClaudiu Beznea1-2/+4
2025-07-08clk: renesas: r9a09g047: Add clock and reset signals for the GBETH IPsJohn Madieu1-0/+64
2025-07-02clk: renesas: r9a09g057: Add XSPI clock/resetLad Prabhakar1-3/+13
2025-07-02clk: renesas: r9a09g056: Add XSPI clock/resetLad Prabhakar2-0/+14
2025-07-02clk: renesas: rzv2h: Add fixed-factor module clocks with status reportingLad Prabhakar2-0/+114
2025-07-02clk: renesas: r9a09g057: Add support for xspi mux and dividerLad Prabhakar1-1/+22
2025-07-02clk: renesas: r9a09g056: Add support for xspi mux and dividerLad Prabhakar1-1/+24
2025-07-02clk: renesas: r9a09g077: Add RIIC module clocksLad Prabhakar1-0/+3
2025-07-02clk: renesas: r9a09g077: Add PLL2 and SDHI clock supportLad Prabhakar1-1/+11
2025-07-02clk: renesas: rzv2h: Drop redundant base pointer from pll_clkLad Prabhakar1-3/+0
2025-07-02clk: renesas: r9a09g057: Add entries for the RSPIsFabrizio Castro1-0/+24
2025-06-26clk: renesas: rzv2h: Add missing include fileFabrizio Castro1-0/+1
2025-06-24clk: renesas: rzv2h: Use devm_kmemdup_array()Raag Jadav1-2/+2
2025-06-19clk: renesas: Add CPG/MSSR support to RZ/N2H SoCLad Prabhakar4-0/+13
2025-06-19clk: renesas: r9a09g077: Add PCLKL core clockLad Prabhakar1-1/+2
2025-06-19clk: renesas: r9a09g047: Add I3C0 clocks and resetsTommaso Merciai1-0/+8
2025-06-13clk: renesas: rzv2h: Fix missing CLK_SET_RATE_PARENT flag for ddiv clocksLad Prabhakar1-0/+1
2025-06-10clk: renesas: rzg2l: Rename mstp_clock to mod_clockGeert Uytterhoeven1-22/+22
2025-06-10clk: renesas: r9a09g056: Add clock and reset entries for USB2.0Lad Prabhakar1-0/+10
2025-06-10clk: renesas: rzg2l: Drop MSTOP based power domain supportClaudiu Beznea2-242/+17
2025-06-10clk: renesas: r9a08g045: Drop power domain instantiationClaudiu Beznea1-123/+93
2025-06-10clk: renesas: rzg2l: Add support for MSTOP in clock enable/disable APIClaudiu Beznea6-266/+517
2025-06-10clk: renesas: rzg2l: Add macro to loop through module clocksClaudiu Beznea1-9/+9
2025-06-10clk: renesas: Add support for R9A09G077 SoCThierry Bultel5-2/+346
2025-06-10clk: renesas: Pass sub struct of cpg_mssr_priv to cpg_clk_registerThierry Bultel10-71/+88
2025-06-10clk: renesas: rzg2l: Move pointers after hw memberClaudiu Beznea1-4/+4
2025-06-10clk: renesas: rzg2l: Postpone updating priv->clks[]Claudiu Beznea1-4/+4
2025-06-10clk: renesas: r9a09g056: Add clocks and resets for Mali-G31 GPULad Prabhakar1-0/+16
2025-06-10clk: renesas: r9a09g056: Add clock and reset entries for WDT controllersLad Prabhakar1-0/+20
2025-06-10clk: renesas: r9a09g056: Add clock and reset entries for RIIC controllersLad Prabhakar1-0/+27
2025-06-10clk: renesas: r9a09g056-cpg: Add clock and reset entries for OSTM instancesLad Prabhakar1-0/+26
2025-06-10clk: renesas: r9a09g056-cpg: Add clock and reset entries for GBETH0/1Lad Prabhakar1-0/+66
2025-06-10clk: renesas: r9a09g057: Add clock and reset entries for GBETH0/1Lad Prabhakar2-0/+71
2025-06-10clk: renesas: rzv2h: Skip monitor checks for external clocksLad Prabhakar2-6/+41
2025-05-08clk: renesas: r9a09g047: Add XSPI clock/resetBiju Das1-0/+12
2025-05-08clk: renesas: r9a09g047: Add support for xspi mux and dividerBiju Das2-1/+33
2025-05-05clk: renesas: Use str_on_off() helperGeert Uytterhoeven2-2/+4
2025-04-22clk: renesas: r9a09g057: Add clock and reset entries for USB2Lad Prabhakar1-1/+19
2025-04-22clk: renesas: rzv2h: Use both CLK_ON and CLK_MON bits for clock state validationLad Prabhakar1-3/+6
2025-04-22clk: renesas: rzv2h: Use str_on_off() helper in rzv2h_mod_clock_endisable()Lad Prabhakar1-1/+2
2025-04-22clk: renesas: rzv2h: Support static dividers without RMWBiju Das2-1/+16
2025-04-22clk: renesas: rzv2h: Add macro for defining static dividersLad Prabhakar2-0/+13
2025-04-22clk: renesas: rzv2h: Add support for static mux clocksLad Prabhakar2-0/+53
2025-04-22clk: renesas: r9a09g047: Add clock and reset entries for GE3DTommaso Merciai1-0/+11
2025-04-22clk: renesas: rzv2h: Fix a typoBiju Das1-1/+1
2025-04-14clk: renesas: rzv2h: Add support for RZ/V2N SoCLad Prabhakar5-0/+165
2025-04-14clk: renesas: rzv2h: Sort compatible list based on SoC part numberLad Prabhakar1-6/+6
2025-04-14clk: renesas: rzv2h: Simplify rzv2h_cpg_assert()/rzv2h_cpg_deassert()Tommaso Merciai1-19/+15
2025-04-14clk: renesas: rzv2h: Improve rzv2h_ddiv_set_rate()Tommaso Merciai1-6/+0
2025-04-08clk: renesas: r9a09g057: Add clock and reset entries for GE3DLad Prabhakar2-0/+16