kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2025-01-07	clk: renesas: r9a09g057: Add clock and reset entries for GIC	Lad Prabhakar	1	-0/+4
2025-01-07	clk: renesas: r9a09g057: Add reset entry for SYS	Lad Prabhakar	1	-0/+1
2025-01-07	clk: renesas: r8a779g0: Add VSPX clocks	Jacopo Mondi	1	-0/+2
2025-01-07	clk: renesas: r8a779g0: Add FCPVX clocks	Jacopo Mondi	1	-0/+2
2025-01-07	clk: renesas: r9a09g047: Add I2C clocks/resets	Biju Das	1	-0/+32
2025-01-07	clk: renesas: r9a09g047: Add CA55 core clocks	Biju Das	1	-0/+16
2025-01-07	clk: renesas: rzv2h: Add support for RZ/G3E SoC	Biju Das	5	-1/+116
2025-01-07	clk: renesas: rzv2h: Add MSTOP support	Biju Das	3	-79/+252
2024-12-10	clk: renesas: r9a08g045: Add clocks, resets and power domain support for the ...	Claudiu Beznea	1	-0/+7
2024-12-10	clk: renesas: r8a779h0: Add display clocks	Tomi Valkeinen	1	-0/+4
2024-12-10	clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets	Lad Prabhakar	2	-0/+51
2024-12-10	clk: renesas: rzv2h: Add selective Runtime PM support for clocks	Lad Prabhakar	2	-7/+49
2024-12-10	clk: renesas: r9a06g032: Use BIT macro consistently	Wolfram Sang	1	-1/+1
2024-12-10	clk: renesas: r9a06g032: Add restart handler	Wolfram Sang	1	-0/+27
2024-12-03	clk: renesas: r9a08g045: Add clock, reset and power domain for the remaining ...	Claudiu Beznea	1	-0/+20
2024-12-03	clk: renesas: r9a08g045: Add clocks, resets and power domains support for SSI	Claudiu Beznea	1	-0/+20
2024-12-03	clk: renesas: cpg-mssr: Fix 'soc' node handling in cpg_mssr_reserved_init()	Javier Carrasco	1	-1/+1
2024-11-06	clk: renesas: vbattb: Add VBATTB clock driver	Claudiu Beznea	3	-0/+211
2024-11-03	clk: renesas: rzg2l: Fix FOUTPOSTDIV clk	Biju Das	1	-5/+6
2024-10-25	clk: renesas: r9a08g045: Add power domain for RTC	Claudiu Beznea	1	-0/+2
2024-10-25	clk: renesas: r9a08g045: Mark the watchdog and always-on PM domains as IRQ safe	Claudiu Beznea	1	-2/+3
2024-10-25	clk: renesas: rzg2l-cpg: Use GENPD_FLAG_* flags instead of local ones	Claudiu Beznea	3	-43/+24
2024-10-25	clk: renesas: rzg2l-cpg: Move PM domain power on in rzg2l_cpg_pd_setup()	Claudiu Beznea	1	-18/+23
2024-10-14	clk: renesas: r8a779h0: Drop CLK_PLL2_DIV2 to clarify ZCn clocks	Geert Uytterhoeven	1	-6/+4
2024-10-07	clk: renesas: r9a09g057: Add clock and reset entries for ICU	Fabrizio Castro	1	-0/+2
2024-10-07	clk: renesas: r9a09g057: Add CA55 core clocks	Lad Prabhakar	2	-0/+21
2024-10-01	clk: renesas: Remove duplicate and trailing empty lines	Marek Vasut	7	-8/+0
2024-09-22	clk: Switch back to struct platform_driver::remove()	Uwe Kleine-König	1	-1/+1
2024-09-22	Merge branches 'clk-assigned-rates', 'clk-renesas' and 'clk-scmi' into clk-next	Stephen Boyd	14	-187/+1526
2024-09-02	clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT	Lad Prabhakar	2	-0/+88
2024-09-02	clk: renesas: rzv2h: Add support for dynamic switching divider clocks	Lad Prabhakar	2	-3/+201
2024-09-02	clk: renesas: r9a08g045: Add clocks, resets and power domains for USB	Claudiu Beznea	1	-0/+17
2024-08-20	clk: renesas: r8a779h0: Add CANFD clock	Cong Dang	1	-0/+1
2024-08-20	clk: renesas: Add RZ/V2H(P) CPG driver	Lad Prabhakar	5	-0/+94
2024-08-03	clk: Use of_property_present()	Rob Herring (Arm)	1	-1/+1
2024-08-02	clk: renesas: Add family-specific clock driver for RZ/V2H(P)	Lad Prabhakar	4	-0/+838
2024-08-02	clk: renesas: r8a779h0: Add PWM clock	Cong Dang	1	-0/+1
2024-07-30	clk: renesas: rcar-gen4: Remove unused default PLL2/3/4/6 configs	Geert Uytterhoeven	5	-28/+20
2024-07-30	clk: renesas: rcar-gen4: Remove unused fixed PLL clock types	Geert Uytterhoeven	2	-24/+0
2024-07-30	clk: renesas: rcar-gen4: Remove unused variable PLL2 clock type	Geert Uytterhoeven	2	-10/+0
2024-07-30	clk: renesas: r8a779h0: Model PLL1/2/3/4/6 as fractional PLLs	Geert Uytterhoeven	1	-5/+5
2024-07-30	clk: renesas: r8a779g0: Model PLL1/3/4/6 as fractional PLLs	Geert Uytterhoeven	1	-7/+7
2024-07-30	clk: renesas: r8a779f0: Model PLL1/2/3/6 as fractional PLLs	Geert Uytterhoeven	1	-6/+6
2024-07-30	clk: renesas: r8a779a0: Use defines for PLL control registers	Geert Uytterhoeven	1	-4/+9
2024-07-30	clk: renesas: rcar-gen4: Add support for fractional 9.24 PLLs	Geert Uytterhoeven	2	-0/+44
2024-07-30	clk: renesas: rcar-gen4: Add support for fixed variable PLLs	Geert Uytterhoeven	2	-10/+26
2024-07-30	clk: renesas: rcar-gen4: Add support for variable fractional PLLs	Geert Uytterhoeven	2	-7/+18
2024-07-30	clk: renesas: rcar-gen4: Add support for fractional multiplication	Geert Uytterhoeven	1	-16/+55
2024-07-30	clk: renesas: rcar-gen4: Use defines for common CPG registers	Geert Uytterhoeven	5	-21/+27
2024-07-30	clk: renesas: rcar-gen4: Use FIELD_GET()	Geert Uytterhoeven	2	-5/+11