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path: root/drivers/clk/meson/clk-mpll.c
AgeCommit message (Expand)AuthorFilesLines
2018-03-13clk: meson: split divider and gate part of mpllJerome Brunet1-44/+0
2018-03-13clk: meson: migrate mplls clocks to clk_regmapJerome Brunet1-65/+37
2018-02-12clk: meson: add axg misc bit to the mpll driverJerome Brunet1-0/+7
2017-12-24clk: meson: mpll: use 64-bit maths in params_from_rateMartin Blumenstingl1-1/+1
2017-08-01clk: meson: mpll: fix mpll0 fractional part ignoredJerome Brunet1-0/+7
2017-04-07clk: meson: mpll: use 64bit math in rate_from_paramsMartin Blumenstingl1-1/+1
2017-04-07clk: meson: mpll: fix division by zero in rate_from_paramsMartin Blumenstingl1-11/+15
2017-03-27clk: meson: mpll: correct N2 maximum valueJerome Brunet1-1/+1
2017-03-27clk: meson: mpll: add rw operationJerome Brunet1-5/+147
2016-06-23clk: meson: add mpll supportMichael Turquette1-0/+94