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2024-11-14clk: amlogic: axg-audio: fix Kconfig dependency on RESET_MESON_AUXArnd Bergmann1-1/+1
As in most cases, using 'imply' is wrong here and does not prevent build failures since that code may not be visible to a built-in clk driver: axg-audio.c:(.text+0x15c): undefined reference to `devm_meson_rst_aux_register' Replace the incorrt 'imply' with the necessary 'depends on'. Fixes: 664988eb47dd ("clk: amlogic: axg-audio: use the auxiliary reset driver") Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20241111102932.3209861-1-arnd@kernel.org Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2024-10-14clk: amlogic: axg-audio: use the auxiliary reset driverJerome Brunet1-0/+1
Remove the implementation of the reset driver in axg audio clock driver and migrate to the one provided by the reset framework on the auxiliary bus Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20241008-meson-clk-rst-aux-v2-1-682ab9151f4f@baylibre.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-06-04clk: meson: c3: add c3 clock peripherals controller driverXianwei Zhao1-0/+14
Add the C3 peripherals clock controller driver in the C3 SoC family. [jbrunet: fix Kconfig select order and probe function name] Co-developed-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20240522082727.3029656-6-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-06-04clk: meson: c3: add support for the C3 SoC PLL clockXianwei Zhao1-0/+13
Add the C3 PLL clock controller driver for the Amlogic C3 SoC family. [jbrunet: fixed probe function name] Co-developed-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Chuan Liu <chuan.liu@amlogic.com> Signed-off-by: Xianwei Zhao <xianwei.zhao@amlogic.com> Link: https://lore.kernel.org/r/20240522082727.3029656-5-xianwei.zhao@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-04-10clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCFNeil Armstrong1-0/+1
In order to setup the DSI clock, let's make the unused VCLK2 clock path configuration via CCF. The nocache option is removed from following clocks: - vclk2_sel - vclk2_input - vclk2_div - vclk2 - vclk_div1 - vclk2_div2_en - vclk2_div4_en - vclk2_div6_en - vclk2_div12_en - vclk2_div2 - vclk2_div4 - vclk2_div6 - vclk2_div12 - cts_encl_sel vclk2 and vclk2_div uses the newly introduced vclk regmap driver to handle the enable and reset bits. In order to set a rate on cts_encl via the vclk2 clock path, the NO_REPARENT flag is set on cts_encl_sel & vclk2_sel in order to keep CCF from selection a parent. The parents of cts_encl_sel & vclk2_sel are expected to be defined in DT or manually set by the display driver at some point. The following clock scheme is to be used for DSI: xtal \_ gp0_pll_dco \_ gp0_pll |- vclk2_sel | \_ vclk2_input | \_ vclk2_div | \_ vclk2 | \_ vclk2_div1 | \_ cts_encl_sel | \_ cts_encl -> to VPU LCD Encoder |- mipi_dsi_pxclk_sel \_ mipi_dsi_pxclk_div \_ mipi_dsi_pxclk -> to DSI controller The mipi_dsi_pxclk_div is set as bypass with a single /1 entry in div_table in order to use the same GP0 for mipi_dsi_pxclk and vclk2_input. The SET_RATE_PARENT is only set on the mipi_dsi_pxclk_sel clock so the DSI bitclock is the reference base clock to calculate the vclk2_div value when pixel clock is set on the cts_encl endpoint. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-3-99ecdfdc87fc@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2024-04-10clk: meson: add vclk driverNeil Armstrong1-0/+4
The VCLK and VCLK_DIV clocks have supplementary bits. The VCLK gate has a "SOFT RESET" bit to toggle after the whole VCLK sub-tree rate has been set, this is implemented in the gate enable callback. The VCLK_DIV clocks as enable and reset bits used to disable and reset the divider, associated with CLK_SET_RATE_GATE it ensures the rate is set while the divider is disabled and in reset mode. The VCLK_DIV enable bit isn't implemented as a gate since it's part of the divider logic and vendor does this exact sequence to ensure the divider is correctly set. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20240403-amlogic-v6-4-upstream-dsi-ccf-vim3-v12-2-99ecdfdc87fc@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-10-23clk: meson: S4: select CONFIG_COMMON_CLK_MESON_CLKC_UTILSArnd Bergmann1-0/+2
Without this, the newly added drivers fail to link: aarch64-linux-ld: drivers/clk/meson/s4-pll.o: in function `meson_s4_pll_probe': s4-pll.c:(.text+0x13c): undefined reference to `meson_clk_hw_get' aarch64-linux-ld: drivers/clk/meson/s4-peripherals.o: in function `meson_s4_periphs_probe': s4-peripherals.c:(.text+0xb0): undefined reference to `meson_clk_hw_get' Fixes: e787c9c55eda ("clk: meson: S4: add support for Amlogic S4 SoC PLL clock driver") Reviewed-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Link: https://lore.kernel.org/r/20231023102810.4001943-1-arnd@kernel.org [jbrunet: use 12 char for the Fixes as recommended ] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC peripheral clock controllerYu Tu1-0/+11
Add the peripherals clock controller driver in the S4 SoC family. [jbrunet: remove extra new line at end of s4-peripherals.h] Signed-off-by: Yu Tu <yu.tu@amlogic.com> Link: https://lore.kernel.org/r/20230904075504.23263-5-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-09-27clk: meson: S4: add support for Amlogic S4 SoC PLL clock driverYu Tu1-0/+12
Add the S4 PLL clock controller driver in the S4 SoC family. Signed-off-by: Yu Tu <yu.tu@amlogic.com> Link: https://lore.kernel.org/r/20230904075504.23263-4-yu.tu@amlogic.com Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: migrate axg-audio out of hw_onecell_data to drop NR_CLKSNeil Armstrong1-0/+1
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw in order to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-6-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: migrate meson8b out of hw_onecell_data to drop NR_CLKSNeil Armstrong1-0/+1
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw in order to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-5-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: migrate a1 clock drivers out of hw_onecell_data to drop NR_CLKSNeil Armstrong1-0/+2
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw in order to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-4-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: migrate meson-aoclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong1-0/+1
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw from the meson_aoclk_data struct to finally get rid on the NR_CLKS define. [jbrunet: Fixed whitespace checkpatch warning] Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-3-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: migrate meson-eeclk out of hw_onecell_data to drop NR_CLKSNeil Armstrong1-0/+1
The way hw_onecell_data is declared: struct clk_hw_onecell_data { unsigned int num; struct clk_hw *hws[]; }; makes it impossible to have the clk_hw table declared outside while using ARRAY_SIZE() to determine ".num" due to ".hws" being a flexible array member. Completely move out of hw_onecell_data and add a custom devm_of_clk_add_hw_provider() "get" callback to retrieve the clk_hw from the meson_eeclkc_data struct to finally get rid on the NR_CLKS define. Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-2-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-08-08clk: meson: introduce meson-clkc-utilsNeil Armstrong1-0/+3
Let's introduce a new module called meson-clkc-utils that will contain shared utility functions for all Amlogic clock controller drivers. The first utility function is a replacement of of_clk_hw_onecell_get in order to get rid of the NR_CLKS define in all Amlogic clock drivers. The goal is to move all duplicate probe and init code in this module. [jbrunet: Fixed MODULE_LICENCE checkpatch warning] Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20230607-topic-amlogic-upstream-clkid-public-migration-v2-1-38172d17c27a@linaro.org Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-05-30clk: meson: a1: add Amlogic A1 Peripherals clock controller driverDmitry Rokosov1-0/+10
Introduce Peripherals clock controller for Amlogic A1 SoC family. A1 SoC has four clock controllers on the board: PLL, Peripherals, CPU, and Audio. This patchset adds support for Amlogic A1 Peripherals clock driver and allows to generate clocks for all A1 SoC peripheral IPs. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230523135351.19133-7-ddrokosov@sberdevices.ru Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2023-05-30clk: meson: a1: add Amlogic A1 PLL clock controller driverDmitry Rokosov1-0/+10
Introduce PLL clock controller for Amlogic A1 SoC family. The clock unit is an APB slave module that is designed for generating all of the internal and system clocks. The SoC uses an external 24MHz crystal; there are 4 internal PLLs: SYS_PLL/HIFI_PLL/USB_PLL/(FIXPLL), these PLLs generate 27 clock sources. Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Dmitry Rokosov <ddrokosov@sberdevices.ru> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Link: https://lore.kernel.org/r/20230523135351.19133-5-ddrokosov@sberdevices.ru Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2020-11-23clk: meson: enable building as modulesKevin Hilman1-3/+3
Make it possible to build all clk drivers as modules, but default remains built-in. No functional changes. Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20201118191405.36798-1-khilman@baylibre.com
2020-11-23clk: meson: Kconfig: fix dependency for G12AKevin Hilman1-0/+1
When building only G12A, ensure that VID_PLL_DIV clock driver is selected, otherwise results in this build error: ERROR: modpost: "meson_vid_pll_div_ro_ops" [drivers/clk/meson/g12a.ko] undefined! Fixes: 085a4ea93d54 ("clk: meson: g12a: add peripheral clock controller") Signed-off-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lore.kernel.org/r/20201118190930.34352-1-khilman@baylibre.com
2020-09-10clk: meson: make shipped controller configurableJerome Brunet1-9/+17
Add the necessary bits so unnecessary amlogic clock controllers can be compiled out. This allows to save a few kB when necessary. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20200828154735.435374-1-jbrunet@baylibre.com
2019-08-09clk: meson: add g12a cpu dynamic divider driverNeil Armstrong1-0/+5
Add a clock driver for the cpu dynamic divider, this divider needs to have a flag set before setting the divider value then removed while writing the new value to the register. This drivers implements this behavior and will be used essentially on the Amlogic G12A and G12B SoCs for cpu clock trees. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: remove clk input helperAlexandre Mergnat1-3/+0
The clk input function which allows clock controllers to register a bypass clock from a clock producer is no longer needed anymore since meson clock controllers have migrated to a new parent allocation method. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: remove ee input bypass clocksAlexandre Mergnat1-1/+0
During probe, bypass clocks (i.e. ee-in-xtal) are made from device-tree inputs to provide input clocks which can be access through global name. The cons of this method are the duplicated clocks, means more string comparison. Specify parent directly with device-tree clock name. Remove the bypass clock registration from the ee probe function. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: remove ao input bypass clocksAlexandre Mergnat1-1/+0
During probe, bypass clocks (i.e. ao-in-xtal) are made from device-tree inputs to provide input clocks which can be access through global name. The cons of this method are the duplicated clocks, means more string comparison. Specify parent directly with device-tree clock name. Function to regiter bypass clocks is removed. Input parameters from meson aoclk data structure are deprecated and then deleted since all aoclk files are migrated. Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29clk: meson: axg-audio: migrate to the new parent description methodAlexandre Mergnat1-1/+0
This clock controller use the string comparison method to describe parent relation between the clocks, which is not optimized. A recent patch [0] allows parents to be specified without string names or with device-tree clock name by using a new assignment structure. Migrate to the new way by using .parent_hws where possible (when parent clocks are localy declared in the controller) and use .parent_data otherwise. Remove clk input helper and all bypass clocks (declared in probe function) which are no longer used since we are able to use device-tree clock name directly. [0] commit fc0c209c147f ("clk: Allow parents to be specified without string names") Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com> [jbrunet@baylibre.com: remove CLK_SET_RATE_PARENT from mst muxes] Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-05-21treewide: Add SPDX license identifier - Makefile/KconfigThomas Gleixner1-0/+1
Add SPDX license identifiers to all Make/Kconfig files which: - Have no license information of any form These files fall under the project license, GPL v2 only. The resulting SPDX license identifier is: GPL-2.0-only Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-02-13clk: meson: Add G12A AO Clock + Reset ControllerNeil Armstrong1-0/+2
Add the Amlogic G12A AO Clock and Reset controller driver handling generation of Always-On clocks : - AO Clocks and Reset for Always-On modules - 32K Generation for USB and CEC - SAR ADC controller clock Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Acked-by: Jerome Brunet <jbrunet@baylibre.com> Link: https://lkml.kernel.org/r/20190212162859.20743-3-narmstrong@baylibre.com
2019-02-04clk: meson: factorise meson64 peripheral clock controller driversJerome Brunet1-3/+8
The function used to probe the peripheral clock controller of the arm64 amlogic SoCs is mostly the same. We now have 3 of those controllers so it is time to factorize things a bit. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-5-jbrunet@baylibre.com
2019-02-04clk: meson: g12a: add peripheral clock controllerJian Hu1-0/+12
Add the peripheral clock controller found in the g12a SoC family Signed-off-by: Jian Hu <jian.hu@amlogic.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201145345.6795-4-jbrunet@baylibre.com
2019-02-02clk: meson: rework and clean drivers dependenciesJerome Brunet1-24/+58
Initially, the meson clock directory only hosted 2 controllers drivers, for meson8 and gxbb. At the time, both used the same set of clock drivers so managing the dependencies was not a big concern. Since this ancient time, entropy did its job, controllers with different requirement and specific clock drivers have been added. Unfortunately, we did not do a great job at managing the dependencies between the controllers and the different clock drivers. Some drivers, such as clk-phase or vid-pll-div, are compiled even if they are useless on the target (meson8). As we are adding new controllers, we need to be able to pick a driver w/o pulling the whole thing. The patch aims to clean things up by: * providing a dedicated CONFIG_ for each clock drivers * allowing clock drivers to be compiled as a modules, if possible * stating explicitly which drivers are required by each controller. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-5-jbrunet@baylibre.com
2019-02-02clk: meson: axg-audio does not require sysconJerome Brunet1-1/+1
The axg audio clock controller uses regmap mmio, not syscon. Fixes: 1cd50181750f ("clk: meson: axg: add the audio clock controller driver") Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Link: https://lkml.kernel.org/r/20190201125841.26785-4-jbrunet@baylibre.com
2018-07-09clk: meson: axg: add the audio clock controller driverJerome Brunet1-0/+9
The axg audio clock controller is the clock generation unit for the amlogic audio subsystem of A113 based SoCs. It may be clocked by 8 different plls provided by the primary clock controller and also by 10 slave bit clocks and 10 slave sample clocks which may be provided by external components, such as audio codecs, through the SoC pads. It contains several muxes, dividers and gates which are fed into the the different devices of the audio subsystem. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: add triple phase clock driverJerome Brunet1-0/+5
Add a driver to control the output of the sample clock generator found in the axg audio clock controller. The goal of this driver is to coherently control the phase provided to the different element using the sample clock generator. This simplify the usage of the sample clock generator a lot, without comprising the ability of the SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-07-09clk: meson: clean-up meson clock configurationJerome Brunet1-9/+5
Clean the dependencies in meson clock Kconfig. CLK_AMLOGIC should actually select CLK_REGMAP_MESON which it uses. Also, each platform should select CLK_AMLOGIC, so everything is properly turned on when the platform Kconfig enable each configuration flag Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-15clk: meson-axg: Add AO Clock and Reset controller driverQiufang Dai1-0/+1
Adds a Clock and Reset controller driver for the Always-On part of the Amlogic Meson-AXG SoC. Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-05-15clk: meson: aoclk: refactor common code into dedicated fileYixun Lan1-0/+7
We try to refactor the common code into one dedicated file, while preparing to add new Meson-AXG aoclk driver, this would help us to better share the code by all aoclk drivers. Suggested-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2018-03-13clk: meson: use hhi syscon if availableJerome Brunet1-0/+2
On gxbb and axg, try to get the hhi regmap from the parent DT node, which should be the HHI system controller once the necessary changes have been made in amlogic's DTs Until then, if getting regmap through the system controller fails, the clock controller will fall back to the old way, requesting memory region directly and then registering the regmap itself. This should allow a smooth transition to syscon Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: migrate gates to clk_regmapJerome Brunet1-2/+2
Move meson8b, gxbb and axg clocks using clk_gate to clk_regmap Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: add regmap to the clock controllersJerome Brunet1-0/+2
This change registers a regmap in meson8b, gxbb and axg controllers. The clock are still accessing their registers directly through iomem. Once all clocks handled by these controllers have been move to regmap, the regmap register will be removed and replaced with a syscon request. This is needed because other drivers, such as the HDMI driver, need to access the HHI register region Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: switch gxbb ao_clk to clk_regmapJerome Brunet1-0/+1
Drop the gxbb ao specific regmap based clock and use the meson clk_regmap based clock instead. Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2018-03-13clk: meson: add regmap clocksJerome Brunet1-0/+4
Meson clock controllers need to move the classical iomem registers to regmap. This is triggered because the HHI controllers found on the GXBB and GXL host more than just clocks. To properly handle this, we would like to migrate HHI to syscon. Also GXBB AO clock controller already use regmap, AXG AO and Audio clock controllers will as well. The purpose of this change is to provide a common structure to these meson controllers (and possibly others) for regmap based clocks. This change provides the basic gate, mux and divider, based on the helpers provided by the related generic clocks Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-12-14clk: meson-axg: add clock controller driversQiufang Dai1-0/+8
Add clock controller drivers for Amlogic Meson-AXG SoC. Acked-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Qiufang Dai <qiufang.dai@amlogic.com> Signed-off-by: Yixun Lan <yixun.lan@amlogic.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-08-04clk: meson: meson8b: register the built-in reset controllerMartin Blumenstingl1-0/+1
The clock controller also includes some reset lines. This patch implements a reset controller to assert and de-assert these resets. The reset controller itself is registered early (through CLK_OF_DECLARE_DRIVER) because it is needed very early in the boot process (to start the secondary CPU cores). According to the public S805 datasheet there are two more reset bits in the HHI_SYS_CPU_CLK_CNTL0 register, which are not implemented by this patch (as these seem to be unused in Amlogic's vendor Linux kernel sources and their u-boot tree): - bit 15: GEN_DIV_SOFT_RESET - bit 14: SOFT_RESET All information was taken from the public S805 Datasheet and Amlogic's vendor GPL kernel sources. This patch is based on an earlier version submitted by Carlo Caione. Suggested-by: Carlo Caione <carlo@endlessm.com> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2017-06-17Merge tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson into ↵Stephen Boyd1-3/+3
clk-next Pull Amlogic clk driver updates from Jerome Brunet: * Expose more clock gate on meson8 (SAR ADC, RNG, USB, SDIO, ETH) * Add new compatible to the meson8 clock controller for meson8b * Add missing parents to gxbb clk81 * tag 'meson-clk-for-4.13-2' of git://github.com/BayLibre/clk-meson: clk: meson: gxbb: add all clk81 parents clk: meson: meson8b: add compatibles for Meson8 and Meson8m2 clk: meson8b: export the ethernet gate clock clk: meson8b: export the USB clocks clk: meson8b: export the gate clock for the HW random number generator clk: meson8b: export the SDIO clock clk: meson8b: export the SAR ADC clocks
2017-06-12clk: meson: meson8b: add compatibles for Meson8 and Meson8m2Martin Blumenstingl1-3/+3
The clock controller on Meson8, Meson8b and Meson8m2 is very similar based on the code from the Amlogic GPL kernel sources. Add separate compatibles for each SoC to make sure that we can easily implement all the small differences for each SoC later on. In general the Meson8 and Meson8m2 seem to be almost identical as they even share the same mach-meson8 directory in Amlogic's GPL kernel sources. The main clocks on Meson8, Meson8b and Meson8m2 are very similar, because they are all using the same PLL values, 90% of the clock gates are the same (the actual diffstat of the mach-meson8/clock.c and mach-meson8b/clock.c files is around 30 to 40 lines, when excluding all commented out code). The difference between the Meson8 and Meson8b clock gates seem to be: - Meson8 has AIU_PCLK, HDMI_RX, VCLK2_ENCT, VCLK2_ENCL, UART3, CSI_DIG_CLKIN gates which don't seem to be available on Meson8b - the gate on Meson8 for bit 7 seems to be named "_1200XXX" instead of "PERIPHS_TOP" (on Meson8b) - Meson8b has a SANA gate which doesn't seem to exist on Meson8 (or on Meson8 the same bit is used by the UART3 gate in Amlogic's GPL kernel sources) None of these gates is added for now, since it's unclear whether these definitions are actually correct (the VCLK2_ENCT gate for example is defined, but only used in some commented block). The main difference between all three SoCs seem to be the video (VPU) clocks. Apart from different supported clock rates (according to vpu.c in mach-meson8 and mach-meson8b from Amlogic's GPL kernel sources) the most notable difference is that Meson8m2 has a GP_PLL clock and a mux (probably the same as on the Meson GX SoCs) to support glitch-free (clock rate) switching. None of these VPU clocks are not supported by our mainline meson8b clock driver yet though. Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com> Acked-by: Rob Herring <robh@kernel.org> Acked-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2017-05-16clk: meson: gxbb: fix build error without RESET_CONTROLLERTobias Regnery1-0/+1
With CONFIG_RESET_CONTROLLER=n we see the following link error in the meson gxbb clk driver: drivers/built-in.o: In function 'gxbb_aoclkc_probe': drivers/clk/meson/gxbb-aoclk.c:161: undefined reference to 'devm_reset_controller_register' Fix this by selecting the reset controller subsystem. Fixes: f8c11f79912d ("clk: meson: Add GXBB AO Clock and Reset controller driver") Signed-off-by: Tobias Regnery <tobias.regnery@gmail.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com> [narmstrong: Added fixes-by tag] Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
2016-06-23clk: gxbb: add AmLogic GXBB clk controller driverMichael Turquette1-0/+7
The gxbb clock controller is the primary clock generation unit for the AmLogic GXBB SoC. It is clocked by a fixed 24MHz xtal, contains several PLLs and the usual post-dividers, muxes, dividers and leaf gates that are fed into various IP blocks in the SoC. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
2016-06-23clk: meson: only build selected platformsMichael Turquette1-0/+12
Break the AmLogic clock code up so that only the necessary parts are compiled and linked. The core code is selected by both arm and arm64 builds with COMMON_CLK_AMLOGIC. The individual drivers have their own config options as well. Tested-by: Kevin Hilman <khilman@baylibre.com> Signed-off-by: Michael Turquette <mturquette@baylibre.com>
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-12 04:35:44 +0300