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path: root/drivers/clk/mediatek/clk-pll.h
AgeCommit message (Expand)AuthorFilesLines
2026-02-27clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocksNicolas Frattaroli1-0/+1
2025-10-06Merge branch 'clk-determine-rate' into clk-nextStephen Boyd1-2/+1
2025-09-21clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENCLaura Nao1-0/+4
2025-09-21clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable controlLaura Nao1-0/+4
2025-09-08clk: mediatek: pll: convert from round_rate() to determine_rate()Brian Masney1-2/+1
2024-01-04clk: mediatek: add pcw_chg_bit control for PLLs of MT7988Sam Shih1-0/+1
2022-11-29clk: mediatek: Export PLL operations symbolsJohnson Wang1-0/+55
2022-05-20clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai1-3/+3
2022-02-17clk: mediatek: pll: Implement error handling in register APIChen-Yu Tsai1-3/+3
2022-02-17clk: mediatek: pll: Implement unregister APIChen-Yu Tsai1-0/+2
2022-02-17clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai1-0/+55