| Age | Commit message (Expand) | Author | Files | Lines |
|---|---|---|---|---|
| 2026-02-27 | clk: mediatek: Add mfg_eb as parent to mt8196 mfgpll clocks | Nicolas Frattaroli | 1 | -0/+1 |
| 2025-10-06 | Merge branch 'clk-determine-rate' into clk-next | Stephen Boyd | 1 | -2/+1 |
| 2025-09-21 | clk: mediatek: clk-pll: Add ops for PLLs using set/clr regs and FENC | Laura Nao | 1 | -0/+4 |
| 2025-09-21 | clk: mediatek: clk-pll: Add set/clr regs for shared PLL enable control | Laura Nao | 1 | -0/+4 |
| 2025-09-08 | clk: mediatek: pll: convert from round_rate() to determine_rate() | Brian Masney | 1 | -2/+1 |
| 2024-01-04 | clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 | Sam Shih | 1 | -0/+1 |
| 2022-11-29 | clk: mediatek: Export PLL operations symbols | Johnson Wang | 1 | -0/+55 |
| 2022-05-20 | clk: mediatek: Replace 'struct clk' with 'struct clk_hw' | Chen-Yu Tsai | 1 | -3/+3 |
| 2022-02-17 | clk: mediatek: pll: Implement error handling in register API | Chen-Yu Tsai | 1 | -3/+3 |
| 2022-02-17 | clk: mediatek: pll: Implement unregister API | Chen-Yu Tsai | 1 | -0/+2 |
| 2022-02-17 | clk: mediatek: pll: Split definitions into separate header file | Chen-Yu Tsai | 1 | -0/+55 |
