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path: root/drivers/clk/mediatek/clk-mt2712.c
AgeCommit message (Expand)AuthorFilesLines
2022-06-16clk: mediatek: reset: Add new register reset function with deviceRex-BC Chen1-2/+2
2022-06-16clk: mediatek: reset: Support nonsequence base offsets of reset registersRex-BC Chen1-4/+7
2022-06-16clk: mediatek: reset: Revise structure to control reset registerRex-BC Chen1-2/+17
2022-06-16clk: mediatek: reset: Merge and revise reset register functionRex-BC Chen1-2/+2
2022-05-20clk: mediatek: Replace 'struct clk' with 'struct clk_hw'Chen-Yu Tsai1-14/+14
2022-05-19clk: mediatek: use en_mask as a pure div_en_maskChun-Jie Chen1-15/+15
2022-02-17clk: mediatek: pll: Split definitions into separate header fileChen-Yu Tsai1-1/+2
2019-10-17clk: mediatek: mt2712: use devm_platform_ioremap_resource() to simplify codeYueHaibing1-4/+2
2019-05-30treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 174Thomas Gleixner1-9/+1
2019-03-08Merge branches 'clk-typo', 'clk-json-schema', 'clk-mtk-2712-eco' and 'clk-roc...Stephen Boyd1-2/+6
2019-02-22clk: mediatek: fix platform_no_drv_owner.cocci warningsYueHaibing1-1/+0
2019-02-06clk: mediatek: update clock driver of MT2712Weiyi Lu1-2/+6
2018-03-20clk: mediatek: update clock driver of MT2712Weiyi Lu1-14/+55
2017-11-02clk: mediatek: Add MT2712 clock supportweiyi.lu@mediatek.com1-0/+1435