kernel/linux.git - Linux kernel stable tree (mirror)

Age	Commit message (Expand)	Author	Files	Lines
2022-05-18	clk: ingenic: Allow specifying common clock flags	Aidan MacDonald	1	-1/+1
2021-11-03	clk: ingenic: Fix bugs with divided dividers	Paul Cercueil	1	-3/+3
2021-06-28	clk: ingenic: Support overriding PLLs M/N/OD calc algorithm	Paul Cercueil	1	-13/+27
2021-06-28	clk: ingenic: Remove pll_info.no_bypass_bit	Paul Cercueil	1	-2/+2
2021-06-28	clk: ingenic: Read bypass register only when there is one	Paul Cercueil	1	-8/+11
2021-06-28	clk: Support bypassing dividers	Paul Cercueil	1	-11/+22
2020-12-20	clk: ingenic: Fix divider calculation with div tables	Paul Cercueil	1	-4/+10
2020-10-14	clk: ingenic: Respect CLK_SET_RATE_PARENT in .round_rate	Paul Cercueil	1	-0/+2
2020-10-14	clk: ingenic: Don't tag custom clocks with CLK_SET_RATE_PARENT	Paul Cercueil	1	-7/+7
2020-10-14	clk: ingenic: Don't use CLK_SET_RATE_GATE for PLL	Paul Cercueil	1	-2/+7
2020-10-14	clk: ingenic: Use readl_poll_timeout instead of custom loop	Paul Cercueil	1	-26/+29
2020-10-14	clk: ingenic: Use to_clk_info() macro for all clocks	Paul Cercueil	1	-39/+15
2020-05-29	clk: Ingenic: Adjust cgu code to make it compatible with X1830.	周琰杰 (Zhou Yanjie)	1	-3/+13
2020-05-29	clk: Ingenic: Remove unnecessary spinlock when reading registers.	周琰杰 (Zhou Yanjie)	1	-11/+1
2019-07-17	Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/cl...	Linus Torvalds	1	-6/+35
2019-06-07	clk: ingenic: Add support for divider tables	Paul Cercueil	1	-6/+35
2019-05-30	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 157	Thomas Gleixner	1	-10/+1
2019-05-15	clk: Remove io.h from clk-provider.h	Stephen Boyd	1	-0/+1
2019-02-26	clk: ingenic: Remove set but not used variable 'enable'	YueHaibing	1	-2/+1
2019-02-22	clk: ingenic: Fix round_rate misbehaving with non-integer dividers	Paul Cercueil	1	-5/+5
2018-06-02	clk: ingenic: Support specifying "wait for clock stable" delay	Paul Cercueil	1	-0/+3
2018-06-02	clk: ingenic: Add support for clocks whose gate bit is inverted	Paul Cercueil	1	-2/+3
2018-01-19	clk: ingenic: Add code to enable/disable PLLs	Paul Cercueil	1	-15/+74
2018-01-19	clk: ingenic: support PLLs with no bypass bit	Paul Cercueil	1	-1/+2
2018-01-19	clk: ingenic: Fix recalc_rate for clocks with fixed divider	Paul Cercueil	1	-0/+2
2017-11-03	Update MIPS email addresses	Paul Burton	1	-1/+1
2016-05-13	clk: ingenic: Allow divider value to be divided	Harvey Hunt	1	-1/+10
2015-07-20	clk: ingenic: Include clk.h	Stephen Boyd	1	-0/+1
2015-06-21	clk: ingenic: add driver for Ingenic SoC CGU clocks	Paul Burton	1	-0/+711