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path: root/drivers/clk/at91/sama7g5.c
AgeCommit message (Expand)AuthorFilesLines
2022-03-08clk: at91: sama7g5: fix parents of PDMCs' GCLKCodrin Ciubotariu1-4/+4
2022-01-25clk: at91: sama7g5: Allow MCK1 to be exported and referenced in DTTudor Ambarus1-1/+7
2021-10-27clk: at91: sama7g5: set low limit for mck0 at 32KHzClaudiu Beznea1-1/+1
2021-10-27clk: at91: sama7g5: remove prescaler part of master clockClaudiu Beznea1-10/+1
2021-10-27clk: at91: clk-master: add notifier for dividerClaudiu Beznea1-1/+1
2021-10-27clk: at91: clk-sam9x60-pll: add notifier for div part of PLLClaudiu Beznea1-2/+11
2021-10-27clk: at91: sama7g5: add securam's peripheral clockClaudiu Beznea1-0/+1
2021-08-29clk: at91: sama7g5: remove all kernel-doc & kernel-doc warningsRandy Dunlap1-7/+7
2021-03-14clk: at91: Trivial typo fixes in the file sama7g5.cBhaskar Chowdhury1-3/+3
2020-12-19clk: at91: sama7g5: register cpu clockClaudiu Beznea1-7/+6
2020-12-19clk: at91: clk-master: re-factor master clockClaudiu Beznea1-2/+11
2020-12-19clk: at91: sama7g5: do not allow cpu pll to go higher than 1GHzClaudiu Beznea1-14/+47
2020-12-19clk: at91: sama7g5: decrease lower limit for MCK0 rateClaudiu Beznea1-1/+1
2020-12-19clk: at91: sama7g5: remove mck0 from parent list of other clocksClaudiu Beznea1-29/+26
2020-12-19clk: at91: clk-sam9x60-pll: allow runtime changes for pllClaudiu Beznea1-17/+50
2020-12-19clk: at91: sama7g5: add 5th divisor for mck0 layout and characteristicsEugen Hristev1-2/+2
2020-12-19clk: at91: sama7g5: allow SYS and CPU PLLs to be exported and referenced in DTEugen Hristev1-2/+4
2020-12-19dt-bindings: clock: at91: add sama7g5 pll definesEugen Hristev1-3/+3
2020-12-19clk: at91: sama7g5: fix compilation errorClaudiu Beznea1-2/+4
2020-07-24clk: at91: sama7g5: add clock support for sama7g5Claudiu Beznea1-0/+1059