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path: root/arch/x86/events/perf_event.h
AgeCommit message (Expand)AuthorFilesLines
2021-06-30perf/x86: Track pmu in per-CPU cpu_hw_eventsKan Liang1-1/+3
2021-06-30perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic contextLike Xu1-0/+6
2021-02-01perf/x86/intel: Support CPUID 10.ECX to disable fixed countersKan Liang1-0/+5
2021-02-01perf/x86/intel: Add perf core PMU support for Sapphire RapidsKan Liang1-1/+11
2021-02-01perf/x86/intel: Filter unsupported Topdown metrics eventKan Liang1-0/+1
2021-01-27perf/intel: Remove Perfmon-v4 counter_freezing supportPeter Zijlstra1-2/+1
2020-11-26Merge remote-tracking branch 'origin/master' into perf/corePeter Zijlstra1-1/+2
2020-11-09perf/x86/intel: Make anythread filter support conditionalStephane Eranian1-0/+1
2020-11-09perf/x86: Reduce stack usage for x86_pmu::drain_pebs()Peter Zijlstra1-1/+1
2020-10-29perf/core: Add support for PERF_SAMPLE_CODE_PAGE_SIZEStephane Eranian1-1/+1
2020-10-06perf/x86: Fix n_metric for cancelled txnPeter Zijlstra1-0/+1
2020-10-06perf/x86: Fix n_pair for cancelled txnPeter Zijlstra1-0/+1
2020-08-18perf/x86/intel: Support TopDown metrics on Ice LakeKan Liang1-0/+13
2020-08-18perf/x86/intel: Generic support for hardware TopDown metricsKan Liang1-0/+37
2020-08-18perf/x86/intel: Fix the name of perf METRICSKan Liang1-1/+1
2020-07-08perf/x86/intel/lbr: Support XSAVES for arch LBR readKan Liang1-0/+7
2020-07-08perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switchKan Liang1-0/+21
2020-07-08perf/x86/intel/lbr: Support Architectural LBRKan Liang1-0/+10
2020-07-08perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all()Kan Liang1-1/+1
2020-07-08perf/x86/intel/lbr: Unify the stored format of LBR informationKan Liang1-4/+2
2020-07-08perf/x86/intel/lbr: Support LBR_CTLKan Liang1-3/+12
2020-07-08perf/x86: Expose CPUID enumeration bits for arch LBRKan Liang1-0/+13
2020-07-08perf/x86/intel/lbr: Use dynamic data structure for task_ctxKan Liang1-1/+6
2020-07-08perf/x86/intel/lbr: Factor out a new struct for generic optimizationKan Liang1-3/+7
2020-07-08perf/x86/intel/lbr: Add the function pointers for LBR save and restoreKan Liang1-0/+6
2020-07-08perf/x86/intel/lbr: Add a function pointer for LBR readKan Liang1-0/+5
2020-07-08perf/x86/intel/lbr: Add a function pointer for LBR resetKan Liang1-0/+17
2020-07-02perf/x86: Keep LBR records unchanged in host context for guest usageLike Xu1-0/+3
2020-07-02perf/x86: Add constraint to create guest LBR event without hw counterLike Xu1-0/+1
2020-07-02perf/x86: Fix variable types for LBR registersWei Wang1-2/+2
2020-04-30x86/perf: Add hardware performance events support for Zhaoxin CPU.CodyYao-oc1-0/+10
2020-01-17perf/x86/amd: Add support for Large Increment per Cycle EventsKim Phillips1-0/+18
2020-01-17perf/x86/amd: Constrain Large Increment per Cycle eventsKim Phillips1-0/+2
2019-10-28perf/x86/intel: Implement LBR callstack context synchronizationAlexey Budankov1-0/+3
2019-10-28perf/core, perf/x86: Introduce swap_task_ctx() method at 'struct pmu'Alexey Budankov1-0/+8
2019-08-28perf/x86/intel: Support PEBS output to PTAlexander Shishkin1-0/+17
2019-07-08Merge tag 'v5.2' into perf/core, to pick up fixesIngo Molnar1-20/+1
2019-06-24perf/x86: Remove pmu->pebs_no_xmm_regsKan Liang1-2/+1
2019-06-24perf/x86: Clean up PEBS_XMM_REGSKan Liang1-18/+0
2019-06-03perf/x86: Use update attribute groups for default attributesJiri Olsa1-3/+0
2019-06-03perf/x86: Use update attribute groups for capsJiri Olsa1-1/+0
2019-06-03perf/x86: Use the new pmu::update_attrs attribute groupJiri Olsa1-1/+1
2019-06-03perf/x86: Get rid of x86_pmu::event_attrsJiri Olsa1-1/+0
2019-05-10perf/x86/intel: Fix INTEL_FLAGS_EVENT_CONSTRAINT* maskingStephane Eranian1-2/+2
2019-04-16perf/x86/intel: Add Icelake supportKan Liang1-0/+2
2019-04-16perf/x86: Support constraint rangesPeter Zijlstra1-6/+37
2019-04-16perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles themAndi Kleen1-0/+1
2019-04-16perf/x86/intel: Support adaptive PEBS v4Kan Liang1-1/+10
2019-04-16perf/x86: Support outputting XMM registersKan Liang1-1/+20
2019-04-16perf/x86/intel: Force resched when TFA sysctl is modifiedStephane Eranian1-0/+1
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