Age | Commit message (Expand) | Author | Files | Lines |
2022-02-16 | x86/perf: Avoid warning for Arch LBR without XSAVE | Andi Kleen | 1 | -0/+3 |
2021-07-07 | Merge tag 'x86-fpu-2021-07-07' of git://git.kernel.org/pub/scm/linux/kernel/g... | Linus Torvalds | 1 | -3/+3 |
2021-06-24 | perf/x86/intel/lbr: Zero the xstate buffer on allocation | Thomas Gleixner | 1 | -1/+2 |
2021-06-23 | x86/fpu/xstate: Sanitize handling of independent features | Thomas Gleixner | 1 | -3/+3 |
2021-06-23 | x86/fpu: Rename "dynamic" XSTATEs to "independent" | Andy Lutomirski | 1 | -3/+3 |
2021-05-18 | perf/x86/lbr: Remove cpuc->lbr_xsave allocation from atomic context | Like Xu | 1 | -6/+20 |
2021-04-28 | Merge tag 'perf-core-2021-04-28' of git://git.kernel.org/pub/scm/linux/kernel... | Linus Torvalds | 1 | -4/+5 |
2021-04-28 | Merge tag 'x86_core_for_v5.13' of git://git.kernel.org/pub/scm/linux/kernel/g... | Linus Torvalds | 1 | -5/+5 |
2021-04-19 | perf/x86: Track pmu in per-CPU cpu_hw_events | Kan Liang | 1 | -4/+5 |
2021-03-18 | x86: Fix various typos in comments | Ingo Molnar | 1 | -1/+1 |
2021-03-15 | perf/x86/intel/ds: Check return values of insn decoder functions | Borislav Petkov | 1 | -5/+5 |
2020-12-15 | Merge tag 'perf-core-2020-12-14' of git://git.kernel.org/pub/scm/linux/kernel... | Linus Torvalds | 1 | -1/+1 |
2020-12-09 | perf/x86/intel/lbr: Fix the return type of get_lbr_cycles() | Kan Liang | 1 | -1/+1 |
2020-10-26 | perf/x86: Avoid TIF_IA32 when checking 64bit mode | Gabriel Krisman Bertazi | 1 | -1/+1 |
2020-08-24 | treewide: Use fallthrough pseudo-keyword | Gustavo A. R. Silva | 1 | -1/+1 |
2020-07-08 | perf/x86/intel/lbr: Support XSAVES for arch LBR read | Kan Liang | 1 | -1/+39 |
2020-07-08 | perf/x86/intel/lbr: Support XSAVES/XRSTORS for LBR context switch | Kan Liang | 1 | -5/+74 |
2020-07-08 | perf/x86: Remove task_ctx_size | Kan Liang | 1 | -1/+0 |
2020-07-08 | perf/x86/intel/lbr: Create kmem_cache for the LBR context data | Kan Liang | 1 | -2/+19 |
2020-07-08 | perf/x86/intel/lbr: Support Architectural LBR | Kan Liang | 1 | -11/+240 |
2020-07-08 | perf/x86/intel/lbr: Factor out intel_pmu_store_lbr | Kan Liang | 1 | -26/+56 |
2020-07-08 | perf/x86/intel/lbr: Factor out rdlbr_all() and wrlbr_all() | Kan Liang | 1 | -16/+50 |
2020-07-08 | perf/x86/intel/lbr: Mark the {rd,wr}lbr_{to,from} wrappers __always_inline | Kan Liang | 1 | -4/+4 |
2020-07-08 | perf/x86/intel/lbr: Unify the stored format of LBR information | Kan Liang | 1 | -10/+10 |
2020-07-08 | perf/x86/intel/lbr: Support LBR_CTL | Kan Liang | 1 | -0/+43 |
2020-07-08 | perf/x86/intel/lbr: Use dynamic data structure for task_ctx | Kan Liang | 1 | -33/+26 |
2020-07-08 | perf/x86/intel/lbr: Factor out a new struct for generic optimization | Kan Liang | 1 | -17/+21 |
2020-07-08 | perf/x86/intel/lbr: Add the function pointers for LBR save and restore | Kan Liang | 1 | -30/+49 |
2020-07-08 | perf/x86/intel/lbr: Add a function pointer for LBR read | Kan Liang | 1 | -6/+3 |
2020-07-08 | perf/x86/intel/lbr: Add a function pointer for LBR reset | Kan Liang | 1 | -17/+3 |
2020-07-02 | perf/x86: Keep LBR records unchanged in host context for guest usage | Like Xu | 1 | -5/+26 |
2020-07-02 | perf/x86: Add constraint to create guest LBR event without hw counter | Like Xu | 1 | -0/+4 |
2020-07-02 | perf/x86/lbr: Add interface to get LBR information | Like Xu | 1 | -0/+20 |
2020-02-11 | perf/x86/intel: Output LBR TOS information correctly | Kan Liang | 1 | -3/+9 |
2020-02-11 | perf/core: Add new branch sample type for HW index of raw branch records | Kan Liang | 1 | -0/+3 |
2019-10-28 | perf/x86/intel: Implement LBR callstack context synchronization | Alexey Budankov | 1 | -0/+23 |
2019-09-03 | perf/x86: Make more stuff static | Valdis Klētnieks | 1 | -1/+1 |
2019-04-16 | perf/x86/lbr: Avoid reading the LBRs when adaptive PEBS handles them | Andi Kleen | 1 | -1/+12 |
2019-04-16 | perf/x86/intel: Support adaptive PEBS v4 | Kan Liang | 1 | -0/+22 |
2019-01-29 | x86/events: Mark expected switch-case fall-throughs | Gustavo A. R. Silva | 1 | -0/+1 |
2018-09-10 | perf/x86/intel: Add support/quirk for the MISPREDICT bit on Knights Landing CPUs | Jacek Tomaka | 1 | -0/+4 |
2018-06-21 | perf/x86/intel/lbr: Optimize context switches for the LBR call stack | Kan Liang | 1 | -1/+23 |
2018-06-21 | perf/x86/intel/lbr: Fix incomplete LBR call stack | Kan Liang | 1 | -6/+26 |
2018-02-15 | x86/cpu: Rename cpu_data.x86_mask to cpu_data.x86_stepping | Jia Zhang | 1 | -1/+1 |
2017-11-02 | License cleanup: add SPDX GPL-2.0 license identifier to files with no license | Greg Kroah-Hartman | 1 | -0/+1 |
2017-07-30 | Merge branch 'perf/urgent' into perf/core, to pick up latest fixes and refres... | Ingo Molnar | 1 | -0/+4 |
2017-07-21 | perf/x86/intel: Add proper condition to run sched_task callbacks | Jiri Olsa | 1 | -0/+4 |
2017-07-19 | perf/x86/intel: Record branch type | Jin Yao | 1 | -1/+51 |
2017-06-30 | perf/x86/intel: Constify the 'lbr_desc[]' array and make a function static | Colin Ian King | 1 | -2/+2 |
2017-04-14 | perf/x86: Avoid exposing wrong/stale data in intel_pmu_lbr_read_32() | Peter Zijlstra | 1 | -0/+3 |