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3 dayskexec: Consolidate machine_kexec_mask_interrupts() implementationEliav Farber1-23/+0
2026-03-04riscv: vector: init vector context with proper vlenbSergey Matyukevich1-4/+8
2026-03-04tracing: Add ftrace_partial_regs() for converting ftrace_regs to pt_regsMasami Hiramatsu (Google)1-0/+14
2026-03-04fgraph: Replace fgraph_ret_regs with ftrace_regsMasami Hiramatsu (Google)3-33/+19
2026-03-04ftrace: Consolidate ftrace_regs accessor functions for archs using pt_regsSteven Rostedt1-0/+1
2026-03-04ftrace: Make ftrace_regs abstract from direct useSteven Rostedt3-24/+27
2026-02-11riscv: Sanitize syscall table indexing under speculationLukas Gerlach1-1/+3
2026-02-06riscv: compat: fix COMPAT_UTS_MACHINE definitionHan Gao1-1/+1
2026-01-17riscv: pgtable: Cleanup useless VA_USER_XXX definitionsGuo Ren (Alibaba DAMO Academy)1-4/+0
2026-01-08lib/crypto: riscv/chacha: Avoid s0/fp registerVivian Wang1-3/+2
2025-12-18RISC-V: KVM: Fix guest page fault within HLV* instructionsFangyu Yu1-0/+22
2025-11-24riscv: acpi: avoid errors caused by probing DT devices when ACPI is usedHan Gao1-2/+5
2025-11-24RISC-V: clear hot-unplugged cores from all task mm_cpumasks to avoid rfence e...Danil Skrebenkov1-0/+1
2025-11-24riscv: Build loader.bin exclusively for Canaan K210Feng Jiang1-1/+1
2025-11-13riscv: ptdump: use seq_puts() in pt_dump_seq_puts() macroJosephine Pfeiffer1-1/+1
2025-11-13riscv: stacktrace: Disable KASAN checks for non-current tasksChunyan Zhang1-2/+19
2025-11-13riscv: bpf: Fix uninitialized symbol 'retval_off'Chenghao Duan1-3/+2
2025-11-02arch: Add the macro COMPILE_OFFSETS to all the asm-offsets.cMenglong Dong1-0/+1
2025-10-29riscv: hwprobe: avoid uninitialized variable use in hwprobe_arch_id()Paul Walmsley1-0/+6
2025-10-29RISC-V: Don't print details of CPUs disabled in DTAnup Patel1-3/+1
2025-10-29RISC-V: Define pgprot_dmacoherent() for non-coherent devicesAnup Patel1-0/+2
2025-10-23riscv: kprobes: Fix probe address validationFabian Vogt1-4/+9
2025-10-15riscv, bpf: Sign extend struct ops return values properlyHengqi Chen1-1/+41
2025-09-19RISC-V: Remove unnecessary include from compat.hPalmer Dabbelt1-1/+0
2025-09-09riscv, bpf: use lw when reading int cpu in bpf_get_smp_processor_idRadim Krčmář1-1/+1
2025-09-09riscv, bpf: use lw when reading int cpu in BPF_MOV64_PERCPU_REGRadim Krčmář1-1/+1
2025-09-09riscv: use lw when reading int cpu in asm_per_cpuRadim Krčmář1-1/+1
2025-09-09riscv: use lw when reading int cpu in new_vmalloc_checkRadim Krčmář1-1/+1
2025-09-09riscv: Only allow LTO with CMODEL_MEDANYNathan Chancellor1-1/+1
2025-09-04RISC-V: KVM: fix stack overrun when loading vlenbRadim Krčmář1-0/+2
2025-08-20mm/ptdump: take the memory hotplug lock inside ptdump_walk_pgd()Anshuman Khandual1-3/+0
2025-07-24riscv: traps_misaligned: properly sign extend value in misaligned load handlerAndreas Schwab1-1/+1
2025-07-24riscv: Enable interrupt during exception handlingNam Cao1-4/+6
2025-07-17riscv: vdso: Exclude .rodata from the PT_DYNAMIC segmentFangrui Song1-1/+1
2025-07-10riscv: cpu_ops_sbi: Use static array for boot_dataVivian Wang1-3/+3
2025-07-06riscv/atomic: Do proper sign extension also for unsigned in arch_cmpxchgSasha Levin1-1/+1
2025-07-06Revert "riscv: misaligned: fix sleeping function called during misaligned acc...Nam Cao1-2/+2
2025-07-06Revert "riscv: Define TASK_SIZE_MAX for __access_ok()"Nam Cao1-1/+0
2025-07-06riscv: add a data fence for CMODX in the kernel modeAndy Chiu1-1/+14
2025-06-27RISC-V: KVM: Don't treat SBI HFENCE calls as NOPsAnup Patel1-2/+2
2025-06-27RISC-V: KVM: Fix the size parameter check in SBI SFENCE callsAnup Patel1-2/+2
2025-06-19riscv: misaligned: fix sleeping function called during misaligned access hand...Nylon Chen1-2/+2
2025-06-19RISC-V: KVM: lock the correct mp_state during resetRadim Krčmář1-2/+2
2025-05-29Fix mis-uses of 'cc-option' for warning disablementLinus Torvalds1-2/+2
2025-05-29riscv: Call secondary mmu notifier when flushing the tlbAlexandre Ghiti1-15/+22
2025-05-29riscv: Allow NOMMU kernels to access all of RAMSamuel Holland2-9/+5
2025-05-22riscv: dts: sophgo: fix DMA data-width configuration for CV18xxZe Huang1-1/+1
2025-05-18riscv: misaligned: enable IRQs while handling misaligned accessesClément Léger1-4/+8
2025-05-18riscv: misaligned: factorize trap handlingClément Léger1-30/+36
2025-05-18riscv: misaligned: Add handling for ZCB instructionsNylon Chen1-0/+17