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2020-01-07riscv: Implement copy_thread_tlsAmanieu d'Antras1-3/+3
2020-01-05riscv: prefix IRQ_ macro names with an RV_ namespacePaul Walmsley1-3/+3
2020-01-03riscv: ftrace: correct the condition logic in function graph tracerZong Li1-1/+1
2019-12-28riscv: reject invalid syscalls below -1David Abdurachmanov1-0/+1
2019-12-28riscv: fix compile failure with EXPORT_SYMBOL() & !MMULuc Van Oostenryck1-3/+0
2019-12-20riscv: fix scratch register clearing in M-mode.Greentime Hu1-1/+1
2019-12-01Merge tag 'seccomp-v5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git...Linus Torvalds1-1/+1
2019-11-27Merge tag 'riscv/for-v5.5-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds18-138/+340
2019-11-26Merge branch 'x86-asm-for-linus' of git://git.kernel.org/pub/scm/linux/kernel...Linus Torvalds1-3/+2
2019-11-26Merge tag 'printk-for-5.5' of git://git.kernel.org/pub/scm/linux/kernel/git/p...Linus Torvalds1-2/+2
2019-11-23Merge branch 'next/nommu' into for-nextPaul Walmsley16-94/+302
2019-11-23Merge branch 'next/isa-string' into for-nextPaul Walmsley1-42/+3
2019-11-18riscv: add nommu supportChristoph Hellwig4-3/+34
2019-11-18riscv: clear the instruction cache and all registers when bootingChristoph Hellwig1-1/+87
2019-11-18riscv: read the hart ID from mhartid on bootDamien Le Moal1-0/+8
2019-11-18riscv: provide native clint access for M-modeChristoph Hellwig5-3/+64
2019-11-14riscv: cleanup the default power off implementationChristoph Hellwig3-2/+18
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig10-86/+91
2019-11-05riscv: enter WFI in default_power_off() if SBI does not shutdownChristoph Hellwig1-1/+2
2019-11-04vmlinux.lds.h: Replace RW_DATA_SECTION with RW_DATAKees Cook1-1/+1
2019-11-04vmlinux.lds.h: Replace RO_DATA_SECTION with RO_DATAKees Cook1-1/+1
2019-11-04vmlinux.lds.h: Move NOTES into RO_DATAKees Cook1-1/+0
2019-10-29riscv: add support for SECCOMP and SECCOMP_FILTERDavid Abdurachmanov2-2/+35
2019-10-28RISC-V: Remove unsupported isa string info printAtish Patra1-42/+3
2019-10-28riscv: for C functions called only from assembly, mark with __visiblePaul Walmsley5-8/+8
2019-10-28riscv: fp: add missing __user pointer annotationsPaul Walmsley1-2/+2
2019-10-28riscv: add missing header file includesPaul Walmsley10-0/+12
2019-10-28riscv: mark some code and data as file-staticPaul Walmsley1-1/+1
2019-10-28riscv: add prototypes for assembly language functions from head.SPaul Walmsley3-0/+25
2019-10-26riscv: cleanup do_trap_breakChristoph Hellwig1-20/+6
2019-10-18riscv: Use pr_warn instead of pr_warningKefeng Wang1-2/+2
2019-10-14riscv: remove the switch statement in do_trap_break()Vincent Chen1-11/+11
2019-10-10RISC-V: entry: Remove unneeded need_resched() loopValentin Schneider1-2/+1
2019-10-07riscv: Correct the handling of unexpected ebreak in do_trap_break()Vincent Chen1-3/+3
2019-10-07riscv: avoid sending a SIGTRAP to a user thread trapped in WARN()Vincent Chen1-1/+1
2019-10-07riscv: avoid kernel hangs when trapped in BUG()Vincent Chen1-3/+3
2019-10-01RISC-V: Clear load reservations while restoring hart contextsPalmer Dabbelt1-1/+20
2019-09-20riscv: Avoid interrupts being erroneously enabled in handle_exception()Vincent Chen1-1/+5
2019-09-20RISC-V: Export kernel symbols for kvmAtish Patra2-0/+2
2019-09-20arch/riscv: disable excess harts before picking main boot hartXiang Wang1-3/+5
2019-09-17Merge tag 'riscv/for-v5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/g...Linus Torvalds8-35/+187
2019-09-17Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/a...Linus Torvalds1-0/+3
2019-09-14riscv: modify the Image header to improve compatibility with the ARM64 headerPaul Walmsley1-2/+2
2019-09-05riscv: cleanup riscv_cpuid_to_hartid_maskChristoph Hellwig1-0/+1
2019-09-05riscv: optimize send_ipi_singleChristoph Hellwig1-1/+7
2019-09-05riscv: cleanup send_ipi_maskChristoph Hellwig1-9/+7
2019-09-05riscv: refactor the IPI codeChristoph Hellwig1-24/+31
2019-09-05riscv: Add support for perf registers samplingMao Han2-0/+45
2019-09-04riscv: Add perf callchain supportMao Han3-3/+98
2019-08-30riscv: Using CSR numbers to access CSRsBin Meng3-8/+8