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4 daysriscv: kgdb: fix several debug register assignment bugsPaul Walmsley1-3/+4
2026-03-25kexec: Consolidate machine_kexec_mask_interrupts() implementationEliav Farber1-23/+0
2026-03-04riscv: vector: init vector context with proper vlenbSergey Matyukevich1-4/+8
2026-03-04fgraph: Replace fgraph_ret_regs with ftrace_regsMasami Hiramatsu (Google)1-11/+13
2026-03-04ftrace: Make ftrace_regs abstract from direct useSteven Rostedt2-15/+15
2026-02-11riscv: Sanitize syscall table indexing under speculationLukas Gerlach1-1/+3
2025-11-24riscv: acpi: avoid errors caused by probing DT devices when ACPI is usedHan Gao1-2/+5
2025-11-24RISC-V: clear hot-unplugged cores from all task mm_cpumasks to avoid rfence e...Danil Skrebenkov1-0/+1
2025-11-13riscv: stacktrace: Disable KASAN checks for non-current tasksChunyan Zhang1-2/+19
2025-11-02arch: Add the macro COMPILE_OFFSETS to all the asm-offsets.cMenglong Dong1-0/+1
2025-10-29riscv: hwprobe: avoid uninitialized variable use in hwprobe_arch_id()Paul Walmsley1-0/+6
2025-10-29RISC-V: Don't print details of CPUs disabled in DTAnup Patel1-3/+1
2025-10-23riscv: kprobes: Fix probe address validationFabian Vogt1-4/+9
2025-09-09riscv: use lw when reading int cpu in new_vmalloc_checkRadim Krčmář1-1/+1
2025-07-24riscv: traps_misaligned: properly sign extend value in misaligned load handlerAndreas Schwab1-1/+1
2025-07-24riscv: Enable interrupt during exception handlingNam Cao1-4/+6
2025-07-17riscv: vdso: Exclude .rodata from the PT_DYNAMIC segmentFangrui Song1-1/+1
2025-07-10riscv: cpu_ops_sbi: Use static array for boot_dataVivian Wang1-3/+3
2025-07-06Revert "riscv: misaligned: fix sleeping function called during misaligned acc...Nam Cao1-2/+2
2025-06-19riscv: misaligned: fix sleeping function called during misaligned access hand...Nylon Chen1-2/+2
2025-05-29Fix mis-uses of 'cc-option' for warning disablementLinus Torvalds1-2/+2
2025-05-18riscv: misaligned: enable IRQs while handling misaligned accessesClément Léger1-4/+8
2025-05-18riscv: misaligned: factorize trap handlingClément Léger1-30/+36
2025-05-18riscv: misaligned: Add handling for ZCB instructionsNylon Chen1-0/+17
2025-05-02riscv: uprobes: Add missing fence.i after building the XOL bufferBjörn Töpel1-8/+2
2025-04-25riscv: KGDB: Remove ".option norvc/.option rvc" for kgdb_compiled_breakWangYuli1-3/+1
2025-04-25riscv: KGDB: Do not inline arch_kgdb_breakpoint()WangYuli1-0/+8
2025-04-25riscv: module: Allocate PLT entries for R_RISCV_PLT32Samuel Holland1-6/+7
2025-04-25riscv: module: Fix out-of-bounds relocation accessSamuel Holland1-1/+1
2025-04-25riscv: Properly export reserved regions in /proc/iomemBjörn Töpel1-1/+35
2025-04-25riscv: Use kvmalloc_array on relocation_hashtableWill Pierce1-4/+5
2025-04-10riscv/kexec_file: Handle R_RISCV_64 in purgatory relocatorYao Zi1-0/+3
2025-03-07riscv: cpufeature: use bitmap_equal() instead of memcmp()Clément Léger1-1/+1
2025-03-07riscv: signal: fix signal_minsigstkszYong-Xuan Wang1-1/+1
2025-03-07riscv: cacheinfo: Use of_property_present() for non-boolean propertiesRob Herring1-6/+6
2025-03-07riscv: signal: fix signal frame sizeYong-Xuan Wang1-6/+0
2025-02-08RISC-V: Mark riscv_v_init() as __initPalmer Dabbelt1-1/+1
2025-01-17riscv: kprobes: Fix incorrect address calculationNam Cao1-1/+1
2025-01-17riscv: Fix sleeping in invalid context in die()Nam Cao1-3/+3
2025-01-17riscv: use local label names instead of global ones in assemblyClément Léger1-10/+10
2025-01-17riscv: stacktrace: fix backtracing through exceptionsClément Léger2-1/+4
2025-01-17riscv: module: remove relocation_head rel_entry member allocationClément Léger1-14/+4
2024-12-19riscv: Fix wrong usage of __pa() on a fixmap addressAlexandre Ghiti1-1/+1
2024-12-05RISC-V: Check scalar unaligned access on all CPUsJesse Taube1-7/+7
2024-12-05RISC-V: Scalar unaligned access emulated on hotplug CPUsJesse Taube1-0/+1
2024-12-05of/fdt: add dt_phys arg to early_init_dt_scan and early_init_dt_verifyUsama Arif1-1/+1
2024-10-25Merge commit 'bf40167d54d5' into fixesPalmer Dabbelt1-0/+1
2024-10-25riscv: Remove duplicated GET_RMChunyan Zhang1-2/+0
2024-10-25riscv: Remove unused GENERATING_ASM_OFFSETSChunyan Zhang1-2/+0
2024-10-25riscv: Use '%u' to format the output of 'cpu'WangYuli1-1/+1