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path: root/arch/riscv/include/asm/csr.h
AgeCommit message (Expand)AuthorFilesLines
2020-05-05RISC-V: Remove N-extension related definesAnup Patel1-3/+0
2020-02-18riscv: set pmp configuration if kernel is running in M-modeGreentime Hu1-0/+12
2020-01-05riscv: prefix IRQ_ macro names with an RV_ namespacePaul Walmsley1-9/+9
2019-11-18riscv: clear the instruction cache and all registers when bootingChristoph Hellwig1-0/+1
2019-11-18riscv: read the hart ID from mhartid on bootDamien Le Moal1-0/+1
2019-11-05riscv: abstract out CSR names for supervisor vs machine modeChristoph Hellwig1-10/+62
2019-06-05treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 286Thomas Gleixner1-9/+1
2019-05-17RISC-V: Access CSRs using CSR numbersAnup Patel1-7/+25
2019-05-17RISC-V: Add interrupt related SCAUSE defines in asm/csr.hAnup Patel1-4/+17
2019-05-17RISC-V: Use tabs to align macro values in asm/csr.hAnup Patel1-38/+38
2018-08-13RISC-V: add a definition for the SIE SEIE bitChristoph Hellwig1-0/+1
2018-01-31riscv: rename sptbr to satpChristoph Hellwig1-7/+7
2018-01-08riscv: rename SR_* constants to match the specChristoph Hellwig1-4/+4
2017-09-27RISC-V: Generic library routines and assemblyPalmer Dabbelt1-0/+132