Age | Commit message (Expand) | Author | Files | Lines |
---|---|---|---|---|
2024-01-10 | riscv: select DCACHE_WORD_ACCESS for efficient unaligned access HW | Jisheng Zhang | 1 | -0/+15 |
2023-06-14 | riscv: mm: stub extable related functions/macros for !MMU | Jisheng Zhang | 1 | -0/+6 |
2022-01-06 | riscv: extable: add a dedicated uaccess handler | Jisheng Zhang | 1 | -0/+23 |
2022-01-06 | riscv: extable: add `type` and `data` fields | Jisheng Zhang | 1 | -8/+17 |
2022-01-06 | riscv: extable: consolidate definitions | Jisheng Zhang | 1 | -0/+33 |