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path: root/arch/arm64/mm/context.c
AgeCommit message (Expand)AuthorFilesLines
2018-02-16arm64: Move BP hardening to check_and_switch_contextMarc Zyngier1-2/+3
2018-02-16arm64: Add skeleton to harden the branch predictor against aliasing attacksWill Deacon1-0/+2
2018-02-16arm64: Move post_ttbr_update_workaround to C codeMarc Zyngier1-0/+9
2018-02-16arm64: mm: Allocate ASIDs in pairsWill Deacon1-8/+17
2018-02-16arm64: mm: Remove pre_ttbr0_update_workaround for Falkor erratum #E1003Will Deacon1-11/+0
2017-03-20arm64: cache: Remove support for ASID-tagged VIVT I-cachesWill Deacon1-3/+0
2017-02-10arm64: Work around Falkor erratum 1003Christopher Covington1-0/+11
2016-11-21arm64: Disable TTBR0_EL1 during normal kernel executionCatalin Marinas1-1/+6
2016-06-21arm64: update ASID limitJean-Philippe Brucker1-3/+6
2016-04-15arm64: Add cpu_panic_kernel helperSuzuki K Poulose1-2/+1
2016-03-04arm64: make mrs_s prefixing implicit in read_cpuidMark Rutland1-1/+1
2016-02-25arm64: Rename cpuid_feature field extract routinesSuzuki K Poulose1-1/+1
2016-02-25arm64: Ensure the secondary CPUs have safe ASIDBits sizeSuzuki K Poulose1-0/+18
2016-02-25arm64: Add helper for extracting ASIDBitsSuzuki K Poulose1-13/+23
2016-02-18arm64: cpufeature: Change read_cpuid() to use sysreg's mrs_s macroJames Morse1-1/+1
2015-11-26arm64: mm: keep reserved ASIDs in sync with mm after multiple rolloversWill Deacon1-12/+26
2015-10-07arm64: mm: kill mm_cpumask usageWill Deacon1-2/+0
2015-10-07arm64: switch_mm: simplify mm and CPU checksWill Deacon1-1/+1
2015-10-07arm64: mm: rewrite ASID allocator and MM context-switching codeWill Deacon1-93/+145
2015-10-07arm64: flush: use local TLB and I-cache invalidationWill Deacon1-2/+2
2015-07-27arm64: force CONFIG_SMP=y and remove redundant #ifdefsWill Deacon1-16/+0
2015-06-12arm64: Do not attempt to use init_mm in reset_context()Catalin Marinas1-0/+8
2012-09-17arm64: Process managementCatalin Marinas1-0/+159
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