| Age | Commit message (Expand) | Author | Files | Lines |
|---|
| 2016-01-25 | ARM: 8471/1: need to save/restore arm register(r11) when it is corrupted | Anson Huang | 1 | -2/+2 |
| 2014-12-10 | ARM: 8222/1: mvebu: enable strex backoff delay | Thomas Petazzoni | 1 | -2/+0 |
| 2014-05-26 | ARM: 8046/1: proc: add support for the Cortex-A17 processor | Will Deacon | 1 | -0/+11 |
| 2014-04-23 | ARM: 8013/1: PJ4B: Add cpu_suspend/cpu_resume hooks for PJ4B | Gregory CLEMENT | 1 | -3/+25 |
| 2014-04-04 | Merge branches 'amba', 'fixes', 'misc', 'mmci', 'unstable/omap-dma' and 'unst... | Russell King | 1 | -1/+12 |
| 2014-02-10 | ARM: 7940/1: add support for the Cortex-A12 processor | Jonathan Austin | 1 | -0/+11 |
| 2014-02-10 | ARM: 7953/1: mm: ensure TLB invalidation is complete before enabling MMU | Will Deacon | 1 | -1/+1 |
| 2013-11-14 | ARM: 7885/1: Save/Restore 64-bit TTBR registers on LPAE suspend/resume | Mahesh Sivasubramanian | 1 | -5/+12 |
| 2013-10-19 | ARM: asm: Add ARM_BE8() assembly helper | Ben Dooks | 1 | -3/+1 |
| 2013-09-05 | Merge branches 'debug-choice', 'devel-stable' and 'misc' into for-linus | Russell King | 1 | -2/+14 |
| 2013-09-02 | ARM: 7823/1: errata: workaround Cortex-A15 erratum 773022 | Will Deacon | 1 | -1/+13 |
| 2013-08-12 | ARM: mm: use inner-shareable barriers for TLB and user cache operations | Will Deacon | 1 | -1/+1 |
| 2013-07-22 | ARM: 7784/1: mm: ensure SMP alternates assemble to exactly 4 bytes with Thumb-2 | Will Deacon | 1 | -5/+6 |
| 2013-07-15 | arm: delete __cpuinit/__CPUINIT usage from all ARM users | Paul Gortmaker | 1 | -2/+0 |
| 2013-06-29 | Merge branch 'devel-stable' into for-next | Russell King | 1 | -6/+21 |
| 2013-06-24 | ARM: 7773/1: PJ4B: Add support for errata 4742 | Gregory CLEMENT | 1 | -3/+31 |
| 2013-06-17 | ARM: 7754/1: Fix the CPU ID and the mask associated to the PJ4B | Gregory CLEMENT | 1 | -2/+2 |
| 2013-06-07 | ARM: add Cortex-R7 Processor Info | Jonathan Austin | 1 | -1/+12 |
| 2013-06-07 | ARM: suspend: fix CPU suspend code for !CONFIG_MMU configurations | Will Deacon | 1 | -5/+9 |
| 2013-05-03 | Merge branches 'devel-stable', 'entry', 'fixes', 'mach-types', 'misc' and 'sm... | Russell King | 1 | -5/+21 |
| 2013-04-17 | ARM: 7695/1: mvebu: Enable pj4b on LPAE compilations | Gregory CLEMENT | 1 | -1/+2 |
| 2013-04-03 | ARM: 7691/1: mm: kill unused TLB_CAN_READ_FROM_L1_CACHE and use ALT_SMP instead | Will Deacon | 1 | -2/+2 |
| 2013-03-22 | ARM: 7678/1: Work around faulty ISAR0 register in some Krait CPUs | Stepan Moskovchenko | 1 | -0/+15 |
| 2013-03-22 | ARM: 7680/1: Detect support for SDIV/UDIV from ISAR0 register | Stephen Boyd | 1 | -2/+2 |
| 2013-01-06 | ARM: 7614/1: mm: fix wrong branch from Cortex-A9 to PJ4b | Haojian Zhuang | 1 | -0/+1 |
| 2013-01-02 | ARM: 7609/1: disable errata work-arounds which access secure registers | Rob Herring | 1 | -1/+2 |
| 2012-12-15 | Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc | Linus Torvalds | 1 | -0/+67 |
| 2012-11-21 | arm: mm: Add support for PJ4B cpu and init routines | Gregory CLEMENT | 1 | -0/+67 |
| 2012-10-18 | ARM: 7553/1: proc-v7: Ensure correct instruction set after cpu_reset | Dave Martin | 1 | -1/+1 |
| 2012-09-25 | ARM: mm: update __v7_setup() to the new LoUIS cache maintenance API | Santosh Shilimkar | 1 | -1/+1 |
| 2012-04-16 | ARM: 7384/1: ThumbEE: Disable userspace TEEHBR access for !CONFIG_ARM_THUMBEE | Jonathan Austin | 1 | -0/+12 |
| 2012-02-27 | ARM: 7345/1: errata: update workaround for A9 erratum #743622 | Will Deacon | 1 | -3/+1 |
| 2012-01-23 | ARM: 7296/1: proc-v7.S: remove HARVARD_CACHE preprocessor guards | Will Deacon | 1 | -6/+0 |
| 2012-01-23 | ARM: 7295/1: cortex-a7: move proc_info out of !CONFIG_ARM_LPAE block | Will Deacon | 1 | -10/+10 |
| 2012-01-05 | Merge branch 'devel-stable' into for-linus | Russell King | 1 | -157/+22 |
| 2012-01-05 | Merge branches 'fixes' and 'misc' into for-linus | Russell King | 1 | -0/+11 |
| 2011-12-24 | ARM: 7197/1: errata: Remove SMP dependency for erratum 751472 | Dave Martin | 1 | -2/+4 |
| 2011-12-11 | ARM: 7202/1: Add Cortex-A7 proc info | Pawel Moll | 1 | -0/+11 |
| 2011-12-08 | ARM: LPAE: MMU setup for the 3-level page table format | Catalin Marinas | 1 | -8/+17 |
| 2011-12-08 | ARM: LPAE: Factor out classic-MMU specific code into proc-v7-2level.S | Catalin Marinas | 1 | -149/+3 |
| 2011-12-06 | ARM: proc-*.S: place cpu_reset functions into .idmap.text section | Will Deacon | 1 | -0/+2 |
| 2011-10-28 | Merge branch 'devel-stable' of http://ftp.arm.linux.org.uk/pub/linux/arm/kern... | Linus Torvalds | 1 | -28/+22 |
| 2011-10-25 | Merge branches 'arnd-randcfg-fixes', 'debug', 'io' (early part), 'l2x0', 'p2v... | Russell King | 1 | -1/+1 |
| 2011-10-01 | ARM: pm: let platforms select cpu_suspend support | Arnd Bergmann | 1 | -1/+1 |
| 2011-09-21 | ARM: pm: no need to save/restore context ID register | Russell King | 1 | -7/+6 |
| 2011-09-21 | ARM: pm: only use preallocated page table during resume | Russell King | 1 | -16/+17 |
| 2011-09-21 | ARM: pm: preallocate a page table for suspend/resume | Russell King | 1 | -6/+0 |
| 2011-08-28 | ARM: pm: avoid writing the auxillary control register for ARMv7 | Russell King | 1 | -1/+3 |
| 2011-08-28 | ARM: pm: some ARMv7 requires a dsb in resume to ensure correctness | Russell King | 1 | -0/+1 |
| 2011-08-28 | ARM: 7066/1: proc-v7: disable SCTLR.TE when disabling MMU | Will Deacon | 1 | -0/+1 |
