summaryrefslogtreecommitdiff
path: root/arch/arm/mm/cache-v7.S
AgeCommit message (Expand)AuthorFilesLines
2022-02-09ARM: cacheflush: avoid clobbering the frame pointerArd Biesheuvel1-22/+18
2021-03-09ARM: 9059/1: cache-v7: get rid of mini-stackArd Biesheuvel1-5/+5
2021-03-09ARM: 9058/1: cache-v7: refactor v7_invalidate_l1 to avoid clobbering r5/r6Ard Biesheuvel1-26/+25
2021-03-09ARM: 9057/1: cache-v7: add missing ISB after cache level selectionArd Biesheuvel1-3/+4
2019-12-08sched/rt, ARM: Use CONFIG_PREEMPTIONThomas Gleixner1-2/+2
2019-07-09Merge tag 'for-linus' of git://git.armlinux.org.uk/~rmk/linux-armLinus Torvalds1-0/+16
2019-06-21ARM: 8862/1: errata: 814220-B-Cache maintenance by set/way operations can exe...Benjamin Gaignard1-0/+3
2019-06-21ARM: 8864/1: Add workaround for I-Cache line size mismatch between CPU coresMarek Szyprowski1-0/+13
2019-06-19treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500Thomas Gleixner1-4/+1
2018-12-05ARM: 8814/1: mm: improve/fix ARM v7_dma_inv_range() unaligned address handlingChris Cole1-3/+5
2017-12-18ARM: 8729/1: Hook B15 readahead cache functions based on processorFlorian Fainelli1-0/+21
2017-02-28scripts/spelling.txt: add "swith" pattern and fix typo instancesMasahiro Yamada1-1/+1
2015-04-15ARM: cache-v7: optimise test for Cortex A9 r0pX devicesRussell King1-4/+3
2015-04-15ARM: cache-v7: optimise branches in v7_flush_cache_louisRussell King1-9/+10
2015-04-15ARM: cache-v7: consolidate initialisation of cache level indexRussell King1-2/+2
2015-04-15ARM: cache-v7: shift CLIDR to extract appropriate field before maskingRussell King1-7/+6
2015-04-15ARM: cache-v7: use movw/movt instructionsRussell King1-5/+6
2014-07-18ARM: convert all "mov.* pc, reg" to "bx reg" for ARMv6+Russell King1-15/+15
2014-05-26ARM: 8055/1: cacheflush: use -st dsb option for ensuring completionWill Deacon1-6/+6
2013-12-29ARM: 7919/1: mm: refactor v7 cache cleaning ops to use way/index sequenceLorenzo Pieralisi1-7/+7
2013-08-12ARM: mm: use inner-shareable barriers for TLB and user cache operationsWill Deacon1-2/+2
2013-06-17ARM: 7752/1: errata: LoUIS bit field in CLIDR register is incorrectJon Medhurst1-0/+8
2013-02-12arm: Add v7_invalidate_l1 to cache-v7.SDinh Nguyen1-0/+46
2012-12-20ARM: 7606/1: cache: flush to LoUU instead of LoUIS on uniprocessor CPUsWill Deacon1-2/+4
2012-10-11Merge branch 'fixes' into for-linusRussell King1-0/+3
2012-09-29ARM: 7541/1: Add ARM ERRATA 775420 workaroundSimon Horman1-0/+3
2012-09-25ARM: mm: rename jump labels in v7_flush_dcache_all functionLorenzo Pieralisi1-7/+7
2012-09-25ARM: mm: implement LoUIS API for cache maintenance opsLorenzo Pieralisi1-0/+36
2012-05-02ARM: 7408/1: cacheflush: return error to userspace when flushing syscall failsWill Deacon1-6/+4
2012-02-16ARM: 7325/1: fix v7 boot with lockdep enabledRabin Vincent1-1/+1
2012-02-09ARM: 7321/1: cache-v7: Disable preemption when reading CCSIDRStephen Boyd1-0/+6
2011-09-17ARM: 7091/1: errata: D-cache line maintenance operation by MVA may not succeedWill Deacon1-0/+20
2011-07-07ARM: mm: cache-v7: Use the new processor struct macrosDave Martin1-13/+2
2011-05-26ARM: 6941/1: cache: ensure MVA is cacheline aligned in flush_kern_dcache_areaWill Deacon1-0/+2
2011-03-31Fix common misspellingsLucas De Marchi1-1/+1
2010-12-13ARM: 6528/1: Use CTR for the I-cache line size on ARMv7Catalin Marinas1-10/+17
2010-10-04ARM: 6405/1: Handle __flush_icache_all for CONFIG_SMP_ON_UPTony Lindgren1-0/+16
2010-10-04ARM: Allow SMP kernels to boot on UP systemsRussell King1-10/+4
2010-05-21ARM: 6139/1: ARMv7: Use the Inner Shareable I-cache on MPSantosh Shilimkar1-0/+4
2010-05-08ARM: 6112/1: Use the Inner Shareable I-cache and BTB ops on ARMv7 SMPCatalin Marinas1-0/+4
2010-02-15ARM: dma-mapping: fix for speculative prefetchingRussell King1-4/+6
2010-02-15ARM: dma-mapping: remove dmac_clean_range and dmac_inv_rangeRussell King1-4/+2
2010-02-15ARM: dma-mapping: provide per-cpu type map/unmap functionsRussell King1-0/+26
2009-12-14ARM: add size argument to __cpuc_flush_dcache_pageRussell King1-6/+7
2009-10-07ARM: 5746/1: Handle possible translation errors in ARMv6/v7 coherent_user_rangeCatalin Marinas1-2/+17
2009-07-24Thumb-2: Implement the unified arch/arm/mm supportCatalin Marinas1-5/+11
2008-11-06ARMv7: Add extra barriers for flush_cache_all compressed/head.SCatalin Marinas1-0/+2
2008-09-01[ARM] 5227/1: Add the ENDPROC declarations to the .S filesCatalin Marinas1-0/+10
2007-05-09[ARM] armv7: add support for ARMv7 cores.Catalin Marinas1-0/+253
generated by cgit v1.2.3 (git 2.39.0) at 2024-12-27 12:40:26 +0300