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Pull MMC updates from Ulf Hansson:
"MMC core:
- Add support for Ultra Capacity SD cards (SDUC, 2TB to 128TB)
- Add support for Ultra High-Speed II SD cards (UHS-II)
- Use a reset control for pwrseq_simple
- Add SD card quirk for broken poweroff notification
- Use GFP_NOIO for SD ACMD22
MMC host:
- bcm2835: Introduce proper clock handling
- mtk-sd: Add support for the Host-Software-Queue interface
- mtk-sd: Add support for the mt7988/mt8196 variants
- mtk-sd: Fix a couple of error paths in ->probe()
- sdhci: Add interface to support UHS-II SD cards
- sdhci_am654: Fixup support for changing the signal voltage level
- sdhci-cadence: Add support for the Microchip PIC64GX variant
- sdhci-esdhc-imx: Add support for eMMC HW-reset
- sdhci-msm: Add support for the X1E80100/IPQ5424/SAR2130P/QCS615 variants
- sdhci-of-arasan: Add support for eMMC HW-reset
- sdhci-pci-gli: Add UHS-II support for the GL9767/GL9755 variants
MEMSTICK:
- A couple of minor updates"
* tag 'mmc-v6.13' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (78 commits)
mmc: pwrseq_simple: Handle !RESET_CONTROLLER properly
mmc: mtk-sd: Fix MMC_CAP2_CRYPTO flag setting
mmc: mtk-sd: Fix error handle of probe function
mmc: core: Correction a warning caused by incorrect type in assignment for UHS-II
mmc: sdhci-esdhc-imx: Update esdhc sysctl dtocv bitmask
mmc: sdhci-esdhc-imx: Implement emmc hardware reset
mmc: core: Correct type in variable assignment for UHS-II
mmc: sdhci-uhs2: correction a warning caused by incorrect type in argument
mmc: sdhci-uhs2: Remove unnecessary variables
mmc: sdhci-uhs2: Correct incorrect type in argument
mmc: sdhci: Make MMC_SDHCI_UHS2 config symbol invisible
mmc: sdhci-uhs2: Remove unnecessary NULL check
mmc: core: Fix error paths for UHS-II card init and re-init
mmc: core: Add error handling of sd_uhs2_power_up()
mmc: core: Simplify sd_uhs2_power_up()
mmc: bcm2835: Introduce proper clock handling
mmc: bcm2835: Fix type of current clock speed
dt-bindings: mmc: Add sdhci compatible for QCS615
mmc: core: Use GFP_NOIO in ACMD22
dt-bindings: mmc: sdhci-msm: Add SAR2130P compatible
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Document the sdhci compatible for Qualcomm QCS615 to support
function for emmc and sd card on the Soc.
Signed-off-by: Yuanjie Yang <quic_yuanjiey@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Message-ID: <20241023092708.604195-2-quic_yuanjiey@quicinc.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Document compatible for the SDHCI Controller on SAR2130P platform.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Message-ID: <20241017-sar2130p-mmc-v1-1-c84da16a001e@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add binding definitions for mmc on MT7988 SoC.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Message-ID: <20241012143826.7690-2-linux@fw-web.de>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Extend the devicetree bindings to include the MT8196 mmc controller,
new tx/rx would be supported from MT8196, and the register settings
of STOP_DLY_SEL and POP_EN_CNT would also be variant.
Signed-off-by: Andy-ld Lu <andy-ld.lu@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Message-ID: <20241011024906.8173-4-andy-ld.lu@mediatek.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Document support for defining a partition table in the mmc-card node.
This is needed if the eMMC doesn't have a partition table written and
the bootloader of the device load data by using absolute offset of the
block device. This is common on embedded device that have eMMC installed
to save space and have non removable block devices.
If an OF partition table is detected, any partition table written in the
eMMC will be ignored and won't be parsed.
eMMC provide a generic disk for user data and if supported (JEDEC 4.4+)
also provide two additional disk ("boot1" and "boot2") for special usage
of boot operation where normally is stored the bootloader or boot info.
New JEDEC version also supports up to 4 GP partition for other usage
called "gp1", "gp2", "gp3", "gp4".
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Link: https://lore.kernel.org/r/20241002221306.4403-7-ansuelsmth@gmail.com
Signed-off-by: Jens Axboe <axboe@kernel.dk>
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Document the SDHCI Controller on the X1E80100 Platform.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20241008-x1e80100-qcp-sdhc-v1-1-dfef4c92ae31@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The IPQ5424 supports eMMC with an SDHCI controller. Add the appropriate
compatible to the documentation.
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Signed-off-by: Sricharan Ramabadhran <quic_srichara@quicinc.com>
Link: https://lore.kernel.org/r/20241004102342.2414317-4-quic_srichara@quicinc.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Since the Cadence sdhci controller is sdhci compatible, the cdns,sdhci.yaml
should ref sdhci-common.yaml to use 'sdhci-caps-mask' property.
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Link: https://lore.kernel.org/r/20240930095449.1813195-17-pierre-henry.moussay@microchip.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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PIC64GX is compatible with cdns,sd4hc without any additional feature
Signed-off-by: Pierre-Henry Moussay <pierre-henry.moussay@microchip.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240930095449.1813195-12-pierre-henry.moussay@microchip.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The device is compatible with rk3588, so add an entry for the 2
compatibles together.
The rk3576 device has a power-domain that needs to be on for the eMMC to
be used. Add it as a requirement.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240904203154.253655-2-detlev.casanova@collabora.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Convert sdhci-atmel documentation to yaml format. The new file will inherit
from sdhci-common.yaml.
Note: Add microchip,sama7g5-sdhci to compatible list as we already use it
in the DT.
Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240902-atmel-sdhci-v4-1-96912fab6b2d@microchip.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add the compatible string for rockchip,rk3576-dw-mshc in its own new
block, for devices that have internal phase settings instead of external
clocks.
Signed-off-by: Detlev Casanova <detlev.casanova@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Link: https://lore.kernel.org/r/010201919996f687-08c1988a-f588-46fa-ad82-023068c316ba-000000@eu-west-1.amazonses.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Properties with variable number of items per each device are expected to
have widest constraints in top-level "properties:" block and further
customized (narrowed) in "if:then:". Add missing top-level constraints
for clocks.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240818172923.121867-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Remove the duplicate compatible entry `renesas,sdhi-r9a09g057` and add a
restriction for clocks and clock-names for the RZ/V2H(P) SoC, which has
four clocks similar to the RZ/G2L SoC.
Reported-by: Geert Uytterhoeven <geert@linux-m68k.org>
Fixes: 32842af74abc ("dt-bindings: mmc: renesas,sdhi: Document RZ/V2H(P) support")
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240805211257.61099-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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SG2042 use Synopsys dwcnshc IP for SD/eMMC controllers.
SG2042 defines 3 clocks for SD/eMMC controllers.
- EMMC_100M/SD_100M for cclk(Card clocks in DWC_mshc), so reuse
existing "core".
- AXI_EMMC/AXI_SD for aclk/hclk(Bus interface clocks in DWC_mshc)
and blck(Core Base Clock in DWC_mshc), these 3 clocks share one
source, so reuse existing "bus".
- 100K_EMMC/100K_SD for cqetmclk(Timer clocks in DWC_mshc), so reuse
existing "timer" which was added for rockchip specified.
Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/9ca450097e5389a38bcd7d8ddf863766df4cea10.1722847198.git.unicorn_wang@outlook.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The SD/MMC block on the RZ/V2H(P) ("R9A09G057") SoC is similar to that
of the R-Car Gen3, but it has some differences:
- HS400 is not supported.
- It has additional SD_STATUS register to control voltage,
power enable and reset.
- It supports fixed address mode.
To accommodate these differences, a SoC-specific 'renesas,sdhi-r9a09g057'
compatible string is added.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240724182119.652080-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add binding for Nuvoton MA35D1 SDHCI controller.
Signed-off-by: Shan-Chun Hung <shanchun1218@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240716004527.20378-2-shanchun1218@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Covert the Spreadtrum SDHCI controller bindings to DT schema.
Rename the file to match compatible. Drop assigned-* properties as
these should not be needed.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Stanislav Jakubek <stano.jakubek@gmail.com>
Link: https://lore.kernel.org/r/ZozY+tOkzK9yfjbo@standask-GA-A55M-S2HP
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Convert layerscape fsl-esdhc binding doc from txt to yaml format.
Addtional change during convert:
- Deprecate "sdhci,wp-inverted", "sdhci,1-bit-only".
- Add "reg" and "interrupts" property.
- Change example "sdhci@2e000" to "mmc@2e000".
- Compatible string require fsl,<chip>-esdhc followed by fsl,esdhc to match
most existed dts file.
- Set clock-frequency to 100mhz in example.
- clock-frequency is not required now.
- Allow dma-coherence
- Add clocks
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Link: https://lore.kernel.org/r/20240613-ls_waring_esdhc-v5-2-36644e2fe21c@nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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According to common mmc core, voltages-ranges should be matrix.
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Reviewed-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240613-ls_waring_esdhc-v5-1-36644e2fe21c@nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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On newer SoCs, the MMC controller can require a power-domain to operate,
add it as optional.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20240605-topic-amlogic-upstream-bindings-fixes-power-domains-mmc-v1-1-4acbb8cc2626@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Document the compatible for SDHCI on SDX75 SoC.
Signed-off-by: Naina Mehta <quic_nainmeht@quicinc.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240523120337.9530-2-quic_nainmeht@quicinc.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The BCM2712 has an SDHCI capable host interface similar to the one found
in other STB chipsets. Add the relevant compatible string.
Signed-off-by: Andrea della Porta <andrea.porta@suse.com>
Reviewed-by: Stefan Wahren <wahrenst@gmx.net>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/f6e0d1fbc6c5e620897b5c65c95147ceaeed1485.1717061147.git.andrea.porta@suse.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Pull MMC updates from Ulf Hansson:
"MMC core:
- Increase the timeout period of the ACMD41 command
- Add card entry for quirks to debugfs
- Add mmc_gpiod_set_cd_config() function
- Store owner from SDIO modules with sdio_register_driver()
MMC host:
- atmel-mci: Some cleanups and a switch to use dev_err_probe()
- renesas_sdhi:
- Add support for RZ/G2L, RZ/G3S and RZ/V2M variants
- Set the SDBUF after reset
- sdhci: Add support for "Tuning Error" interrupts
- sdhci-acpi:
- Add quirk to enable pull-up on the card-detect GPIO on Asus
T100TA
- Disable write protect detection on Toshiba WT10-A
- Fix Lenovo Yoga Tablet 2 Pro 1380 sdcard slot not working
- sdhci_am654:
- Re-work and fix the tuning support for multiple speed-modes
- Add tuning algorithm for delay chain
- sdhci-esdhc-imx: Add NXP S32G3 support
- sdhci-of-dwcmshc:
- Add tuning support for Sophgo CV1800B and SG200X
- Implement SDHCI CQE support
- sdhci-pci-gli: Use the proper pci_set_power_state() instead of
PMCSR writes"
MEMSTICK:
- Convert a couple of drivers to use the ->remove_new() callback"
* tag 'mmc-v6.10' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (59 commits)
mmc: renesas_sdhi: Add compatible string for RZ/G2L family, RZ/G3S, and RZ/V2M SoCs
dt-bindings: mmc: renesas,sdhi: Document RZ/G2L family compatibility
dt-bindings: mmc: renesas,sdhi: Group single const value items into an enum list
mmc: renesas_sdhi: Set the SDBUF after reset
mmc: core: Increase the timeout period of the ACMD41 command
mmc: core: Convert to use __mmc_poll_for_busy() SD_APP_OP_COND too
mmc: atmel-mci: Switch to use dev_err_probe()
mmc: atmel-mci: Incapsulate used to be a platform data into host structure
mmc: atmel-mci: Replace platform device pointer by generic one
mmc: atmel-mci: Use temporary variable for struct device
mmc: atmel-mci: Get rid of platform data leftovers
mmc: sdhci-of-dwcmshc: Add tuning support for Sophgo CV1800B and SG200X
mmc: sdhci-of-dwcmshc: Remove useless "&" of th1520_execute_tuning
mmc: sdhci-s3c: Choose sdhci_ops based on variant
mmc: sdhci_am654: Constify struct sdhci_ops
mmc: sdhci-sprd: Constify struct sdhci_ops
mmc: sdhci-omap: Constify struct sdhci_ops
mmc: sdhci-esdhc-mcf: Constify struct sdhci_ops
mmc: slot-gpio: Use irq_handler_t type
mmc: sdhci-acpi: Add quirk to enable pull-up on the card-detect GPIO on Asus T100TA
...
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- RZ/G2UL and RZ/Five ("r9a07g043")
- RZ/G2L(C) ("r9a07g044")
- RZ/V2L ("r9a07g054")
- RZ/G3S ("r9a08g045")
- RZ/V2M ("r9a09g011")
The SD/MMC Interface in the above listed SoCs is not identical to that of
R-Car Gen3. These SoCs have HS400 disabled and use fixed address mode.
Therefore, we need to apply fixed_addr_mode and hs400_disabled quirks.
Document 'renesas,rzg2l-sdhi' as a generic compatible string for the
above SoCs.
Also now use the 'renesas,rzg2l-sdhi' string in the if check for making
sure the required clocks are present.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20240430145937.133643-3-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Group single const value items into an enum list.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20240430145937.133643-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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access-controllers is an optional property that allows a peripheral to
refer to one or more domain access controller(s).
Description of this property is added to all peripheral binding files of
the peripheral under the STM32 firewall controller. It allows an accurate
representation of the hardware, where various peripherals are connected
to a firewall bus. The firewall can then check the peripheral accesses
before allowing its device to probe.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Alexandre Torgue <alexandre.torgue@foss.st.com>
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Add a compatible string for the SDHC binding of NXP S32G3 platforms. Here
we use "nxp,s32g2-usdhc" as fallback since the s32g2-usdhc
driver works also on S32G3 platforms.
Signed-off-by: Wadim Mueller <wafgo01@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240324214329.29988-4-wafgo01@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add binding and an extra property for Hi3798MV200 DWMMC specific extension.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Link: https://lore.kernel.org/r/20240229-b4-mmc-hi3798mv200-v7-4-10c03f316285@outlook.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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convert the legacy txt binding to modern YAML and rename to
hisilicon,hi3798cv200-dw-mshc.yaml. No semantic change.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Yang Xiwen <forbidden405@outlook.com>
Link: https://lore.kernel.org/r/20240229-b4-mmc-hi3798mv200-v7-3-10c03f316285@outlook.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The fsl-imx-mmc hardware needs two clocks to operate: ipg and per.
Document these required clocks.
This fixes the following schema warning:
imx27-apf27dev.dtb: mmc@10014000: Unevaluated properties are not allowed ('clock-names', 'clocks' were unexpected)
from schema $id: http://devicetree.org/schemas/mmc/fsl-imx-mmc.yaml#
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240222143911.979058-1-festevam@gmail.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Some devices support only the default and the 100MHz case, add the
support for this to the binding to avoid warnings.
Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240221184602.3639619-1-m.felsch@pengutronix.de
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add compatible value for the dwcmshc controller in Sophgo's CV1800B and
SG2002.
Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240217144202.3808-2-jszhang@kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Document support for the SD Card/MMC Interface in the Renesas R-Car V4M
(R8A779H0) SoC.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/fffc5a0a73c4cc8e8d7c5d93679531cc24e006ca.1707915511.git.geert+renesas@glider.be
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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iMX95 and iMX8QM have smmu. Add property "iommus".
Signed-off-by: Frank Li <Frank.Li@nxp.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240201-8qm_smmu-v2-1-3d12a80201a3@nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Same as i.MX93, add i.MX95 SDHC which is compatible with i.MX8MM USDHC.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lore.kernel.org/r/20240122091623.2078089-1-peng.fan@oss.nxp.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux
Pull devicetree updates from Rob Herring:
- Convert FPGA bridge, all TPMs (finally), and Rockchip HDMI bindings
to schemas
- Improvements in Samsung GPU schemas
- A few more cases of dropping unneeded quotes in schemas
- Merge QCom idle-states txt binding into common idle-states schema
- Add X1E80100, SM8650, SM8650, and SDX75 SoCs to QCom Power Domain
Controller
- Add NXP i.mx8dl to SCU PD
- Add synaptics r63353 panel controller
- Clarify the wording around the use of 'wakeup-source' property
- Add a DTS coding style doc
- Add smi vendor prefix
- Fix DT_SCHEMA_FILES incorrect matching of paths outside the kernel
tree
- Disable sysfb (e.g. EFI FB) when simple-framebuffer node is present
- Fix double free in of_parse_phandle_with_args_map()
- A couple of kerneldoc fixes
* tag 'devicetree-for-6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/robh/linux: (37 commits)
of: unittest: Fix of_count_phandle_with_args() expected value message
dt-bindings: fpga: altera: Convert bridge bindings to yaml
dt-bindings: fpga: Convert bridge binding to yaml
dt-bindings: vendor-prefixes: Add smi
dt-bindings: power: Clarify wording for wakeup-source property
of: Fix double free in of_parse_phandle_with_args_map
dt-bindings: ignore paths outside kernel for DT_SCHEMA_FILES
drivers: of: Fixed kernel doc warning
dt-bindings: tpm: Document Microsoft fTPM bindings
dt-bindings: tpm: Convert IBM vTPM bindings to DT schema
dt-bindings: tpm: Convert Google Cr50 bindings to DT schema
dt-bindings: tpm: Consolidate TCG TIS bindings
dt-bindings: display: rockchip,inno-hdmi: Document RK3128 compatible
dt-bindings: arm: Add remote etm dt-binding
dt-bindings: mmc: sdhci-pxa: Fix 'regs' typo
media: dt-bindings: samsung,s5p-mfc: Fix iommu properties schemas
dt-bindings: display: panel: Add synaptics r63353 panel controller
dt-bindings: arm: merge qcom,idle-state with idle-state
dt-bindings: drm: rockchip: convert inno_hdmi-rockchip.txt to yaml
dt-bindings: cache: qcom,llcc: correct QDU1000 reg entries
...
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Pull MMC updates from Ulf Hansson:
"MMC core:
- Don't force a retune before eMMC RPMB switch
- Add optional HS400 tuning in HS400es initialization
- Add a sysfs node to for write-protect-group-size
- Add re-tuning test to the mmc-test module
- Use mrq.sbc to support close-ended ioctl requests
MMC host:
- mmci: Add support for SDIO in-band irqs for the stm32 variant
- mmc_spi: Remove broken support custom DMA mapped buffers
- mtk-sd: Improve and extend the support for tunings
- renesas_sdhi: Document support for the RZ/Five variant
- sdhci_am654: Drop support for the ti,otap-del-sel DT property
- sdhci-brcmstb: Add support for the brcm 74165b0 variant
- sdhci-msm: Add compatibles for IPQ4019 and IPQ8074
- sdhci-of-dwcmshc: Add support for the T-Head TH1520 variant
- sdhci-xenon: Add support for the Marvell ac5 variant"
* tag 'mmc-v6.8' of git://git.kernel.org/pub/scm/linux/kernel/git/ulfh/mmc: (27 commits)
mmc: xenon: Add ac5 support via bounce buffer
dt-bindings: mmc: add Marvell ac5
mmc: sdhci-brcmstb: add new sdhci reset sequence for brcm 74165b0
dt-bindings: mmc: brcm,sdhci-brcmstb: Add support for 74165b0
mmc: core: Do not force a retune before RPMB switch
mmc: core: Add HS400 tuning in HS400es initialization
mmc: sdhci_omap: Fix TI SoC dependencies
mmc: sdhci_am654: Fix TI SoC dependencies
mmc: core: Add wp_grp_size sysfs node
mmc: mmc_test: Add re-tuning test
mmc: mmc_spi: remove custom DMA mapped buffers
dt-bindings: mmc: sdhci-msm: document dedicated IPQ4019 and IPQ8074
dt-bindings: mmc: synopsys-dw-mshc: add iommus for Intel SocFPGA
mmc: mtk-sd: Extend number of tuning steps
dt-bindings: mmc: mtk-sd: add tuning steps related property
mmc: sdhci-omap: don't misuse kernel-doc marker
mmc: mtk-sd: Increase the verbosity of msdc_track_cmd_data
mmc: core: Use mrq.sbc in close-ended ffu
mmc: sdhci_am654: Drop lookup for deprecated ti,otap-del-sel
mmc: sdhci-of-dwcmshc: Use logical OR instead of bitwise OR in dwcmshc_probe()
...
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The correct property name is 'reg' not 'regs'.
Fixes: ae5c0585dfc2 ("dt-bindings: mmc: Convert sdhci-pxa to json-schema")
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231213224219.2191721-1-robh@kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
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Add dt bindings for Marvell AC5/X/IM eMMC controller.
This compatibility string covers the differences in the
AC5/X version of the driver: 31-bit bus limitation and
DDR memory starting at address 0x2_0000_0000, which are handled
by usage of a bounce buffer plus a different DMA mask.
Signed-off-by: Elad Nachman <enachman@marvell.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20240103172803.1826113-2-enachman@marvell.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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With newer sdio controller core used for 74165b0 we need to update
the compatibility with "brcm,bcm74165b0-sdhci".
Signed-off-by: Kamal Dasu <kdasu@broadcom.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Florian Fainelli <florian.fainelli@broadcom.com>
Link: https://lore.kernel.org/r/20240103222338.31447-2-kamal.dasu@broadcom.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add dedicated compatibles for the Qualcomm IPQ4019 and IPQ8074 SoCs,
because usage of generic qcom,sdhci-msm-v4 compatible alone is
deprecated.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231211085830.25380-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The DW MSHC node in Intel SocFPGA ARM64 DTS has iommus property, so
allow it to silence dtbs_check warnings:
socfpga_n5x_socdk.dtb: mmc@ff808000: Unevaluated properties are not allowed ('iommus' was unexpected)
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Link: https://lore.kernel.org/r/20231209171013.249972-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add 'mediatek,tuning-steps' setting. This property will give MSDC
a chance to extend tuning steps up to 64. With more tuning steps,
MSDC may achieve a more optimal calibration result, thus avoiding
potential CRC issues.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Axe Yang <axe.yang@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Link: https://lore.kernel.org/r/20231207063535.29546-2-axe.yang@mediatek.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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The SDHI block on the RZ/Five SoC is identical to one found on the RZ/G2UL
SoC. "renesas,sdhi-r9a07g043" compatible string will be used on the
RZ/Five SoC so to make this clear and to keep this file consistent, update
the comment to include RZ/Five SoC.
No driver changes are required as generic compatible string
"renesas,rcar-gen3-sdhi" will be used as a fallback on RZ/Five SoC.
Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/20231115203254.30544-1-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add gate property in example node for Xilinx platforms which will be used
to ungate the DLL clock. DLL clock is required for higher frequencies like
50MHz, 100MHz and 200MHz.
DLL clock is automatically selected by the SD controller when the SD
output clock frequency is more than 25 MHz.
Signed-off-by: Swati Agarwal <swati.agarwal@amd.com>
Co-developed-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Signed-off-by: Sai Krishna Potthuri <sai.krishna.potthuri@amd.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20231114102321.1147951-1-sai.krishna.potthuri@amd.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Add compatible value for the T-Head TH1520 dwcmshc controller.
Acked-by: Guo Ren <guoren@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Drew Fustini <dfustini@baylibre.com>
Link: https://lore.kernel.org/r/20231109-th1520-mmc-v5-1-018bd039cf17@baylibre.com
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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Use only one and exactly one space around '=' in DTS example.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Serge Semin <fancer.lancer@gmail.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org> # For MMC
Acked-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> #for-iio
Acked-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lore.kernel.org/r/20231124092121.16866-1-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring <robh@kernel.org>
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existing SoC
Samsung Exynos SoC reuses several devices from older designs, thus
historically we kept the old (block's) compatible only. This works fine
and there is no bug here, however guidelines expressed in
Documentation/devicetree/bindings/writing-bindings.rst state that:
1. Compatibles should be specific.
2. We should add new compatibles in case of bugs or features.
Add compatibles specific to each SoC in front of all old-SoC-like
compatibles.
While re-indenting the first enum, put also axis,artpec8-dw-mshc in
alphabetical order.
Reviewed-by: Alim Akhtar <alim.akhtar@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Link: https://lore.kernel.org/r/20231108104343.24192-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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